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Valgrind: r16329 - in /trunk: ./ memcheck/ none/tests/ppc32/ none/tests/ppc64/

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Valgrind: r16329 - in /trunk: ./ memcheck/ none/tests/ppc32/ none/tests/ppc64/

svn-2
Author: carll
Date: Wed May  3 18:28:35 2017
New Revision: 16329

Log:
PPC64 ISA 3.0B, add support for the additional instructions: addex, mffscdrn,
mffscdrni, mffsce, mffscrn, mffscrni, mffsl. vmsumudm.

Additionally, the OV32 and CA32 bits were introduced in ISA 3.0 but
Valgrind add support for setting these bits for ISA 3.0.  The OV32 and CA32
bits must now be set on a number of pre ISA 3.0 instructions.  So now the
instructions produce different results in the XER register.  Thus we need pre
and post ISA 3.0 expect files.  Command line options were added to thee
pre ISA test cases so instructions that didn't change could be run with one
set of command line args.  The instructions that have different XER results
are run using a different set of command line args.  The tests were split into
two, one for instructions that didn't change on for instructions that do
change under ISA 3.0.  We then create ISA3.0 expect files only for the tests
that run differently.  By doing this we minimized the size of the expect files
needed.

Vex commit 3359  Has the source code changes for the instruction and OV32, CS32
support

This commit is all the test case changes, adding the new test case files.

Valgrind bugzilla 378931

Modified:
    trunk/NEWS
    trunk/memcheck/mc_main.c
    trunk/none/tests/ppc32/Makefile.am
    trunk/none/tests/ppc32/jm-insns.c
    trunk/none/tests/ppc32/jm-int.stdout.exp
    trunk/none/tests/ppc32/test_isa_2_06_part2.c
    trunk/none/tests/ppc32/test_isa_2_06_part2.stdout.exp
    trunk/none/tests/ppc32/test_isa_2_06_part2.vgtest
    trunk/none/tests/ppc32/test_isa_2_06_part3.c
    trunk/none/tests/ppc32/test_isa_2_06_part3.stdout.exp
    trunk/none/tests/ppc32/test_isa_2_06_part3.vgtest
    trunk/none/tests/ppc64/Makefile.am
    trunk/none/tests/ppc64/jm-int.stdout.exp
    trunk/none/tests/ppc64/ppc64_helpers.h
    trunk/none/tests/ppc64/test_isa_2_06_part2.stdout.exp
    trunk/none/tests/ppc64/test_isa_2_06_part2.vgtest
    trunk/none/tests/ppc64/test_isa_2_06_part3.stdout.exp
    trunk/none/tests/ppc64/test_isa_2_06_part3.vgtest
    trunk/none/tests/ppc64/test_isa_3_0.c
    trunk/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE
    trunk/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE
    trunk/none/tests/ppc64/test_isa_3_0_other.vgtest

Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Wed May  3 18:28:35 2017
@@ -163,6 +163,7 @@
 379372  UNKNOWN task message [id 3447, to mach_task_self(), reply 0x603]
         (task_register_dyld_shared_cache_image_info)
 379390  unhandled syscall: mach:70 (host_create_mach_voucher_trap)
+378931  Add ISA 3.0B additional isnstructions, add OV32, CA32 setting support
 
 Release 3.12.0 (20 October 2016)
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Modified: trunk/memcheck/mc_main.c
==============================================================================
--- trunk/memcheck/mc_main.c (original)
+++ trunk/memcheck/mc_main.c Wed May  3 18:28:35 2017
@@ -4465,7 +4465,7 @@
 static void mc_post_reg_write ( CorePart part, ThreadId tid,
                                 PtrdiffT offset, SizeT size)
 {
-#  define MAX_REG_WRITE_SIZE 1712
+#  define MAX_REG_WRITE_SIZE 1728
    UChar area[MAX_REG_WRITE_SIZE];
    tl_assert(size <= MAX_REG_WRITE_SIZE);
    VG_(memset)(area, V_BITS8_DEFINED, size);

Modified: trunk/none/tests/ppc32/Makefile.am
==============================================================================
--- trunk/none/tests/ppc32/Makefile.am (original)
+++ trunk/none/tests/ppc32/Makefile.am Wed May  3 18:28:35 2017
@@ -10,6 +10,7 @@
  bug139050-ppc32.vgtest \
  ldstrev.stderr.exp ldstrev.stdout.exp ldstrev.vgtest \
  jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest \
+ jm-int_other.stderr.exp jm-int_other.stdout.exp jm-int_other.vgtest \
  jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest jm-fp.stdout.exp-BE2 \
  jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.stdout.exp_Minus_nan \
  jm-vmx.vgtest \
@@ -32,6 +33,8 @@
  test_isa_2_06_part1.stderr.exp  test_isa_2_06_part1.stdout.exp  test_isa_2_06_part1.vgtest \
  test_isa_2_06_part2.stderr.exp  test_isa_2_06_part2.stdout.exp  test_isa_2_06_part2.vgtest \
  test_isa_2_06_part3.stderr.exp  test_isa_2_06_part3.stdout.exp  test_isa_2_06_part3.vgtest \
+ test_isa_2_06_part2-div.stderr.exp  test_isa_2_06_part2-div.stdout.exp  test_isa_2_06_part2-div.vgtest \
+ test_isa_2_06_part3-div.stderr.exp  test_isa_2_06_part3-div.stdout.exp  test_isa_2_06_part3-div.vgtest \
  test_dfp1.stderr.exp test_dfp1.stdout.exp test_dfp1.vgtest \
  test_dfp2.stderr.exp test_dfp2.stdout.exp test_dfp2.vgtest \
  test_dfp2.stdout.exp_Without_dcffix \

Modified: trunk/none/tests/ppc32/jm-insns.c
==============================================================================
--- trunk/none/tests/ppc32/jm-insns.c (original)
+++ trunk/none/tests/ppc32/jm-insns.c Wed May  3 18:28:35 2017
@@ -7620,7 +7620,10 @@
 #else // #if !defined (USAGE_SIMPLE)
    fprintf(stderr,
            "Usage: jm-insns [OPTION]\n"
-           "\t-i: test integer instructions (default)\n"
+           "\t-i: test integer arithmetic instructions (default)\n"
+           "\t-l: test integer logical instructions (default)\n"
+           "\t-c: test integer compare instructions (default)\n"
+           "\t-L: test integer load/store instructions (default)\n"
            "\t-f: test floating point instructions\n"
            "\t-a: test altivec instructions\n"
            "\t-m: test miscellaneous instructions\n"
@@ -7767,7 +7770,8 @@
 #else // #if !defined (USAGE_SIMPLE)
 ////////////////////////////////////////////////////////////////////////
    /* Simple usage:
-      ./jm-insns -i   => int insns
+      ./jm-insns -i   => int arithmetic insns
+      ./jm-insns -l   => int logical insns
       ./jm-insns -f   => fp  insns
       ./jm-insns -a   => av  insns
       ./jm-insns -m   => miscellaneous insns
@@ -7782,10 +7786,10 @@
    flags.two_args   = 1;
    flags.three_args = 1;
    // Type
-   flags.arith      = 1;
-   flags.logical    = 1;
-   flags.compare    = 1;
-   flags.ldst       = 1;
+   flags.arith      = 0;
+   flags.logical    = 0;
+   flags.compare    = 0;
+   flags.ldst       = 0;
    // Family
    flags.integer    = 0;
    flags.floats     = 0;
@@ -7796,22 +7800,51 @@
    // Flags
    flags.cr         = 2;
 
-   while ((c = getopt(argc, argv, "ifmahvA")) != -1) {
+   while ((c = getopt(argc, argv, "ilcLfmahvA")) != -1) {
       switch (c) {
       case 'i':
+         flags.arith    = 1;
+         flags.integer  = 1;
+         break;
+      case 'l':
+         flags.logical  = 1;
+         flags.integer  = 1;
+         break;
+      case 'c':
+         flags.compare  = 1;
+         flags.integer  = 1;
+         break;
+      case 'L':
+         flags.ldst     = 1;
          flags.integer  = 1;
          break;
       case 'f':
+         flags.arith  = 1;
+         flags.logical  = 1;
+         flags.compare  = 1;
+         flags.ldst     = 1;
          flags.floats   = 1;
          break;
       case 'a':
+         flags.arith    = 1;
+         flags.logical  = 1;
+         flags.compare  = 1;
+         flags.ldst     = 1;
          flags.altivec  = 1;
          flags.faltivec = 1;
          break;
       case 'm':
+         flags.arith    = 1;
+         flags.logical  = 1;
+         flags.compare  = 1;
+         flags.ldst     = 1;
          flags.misc     = 1;
          break;
       case 'A':
+         flags.arith    = 1;
+         flags.logical  = 1;
+         flags.compare  = 1;
+         flags.ldst     = 1;
          flags.integer  = 1;
          flags.floats   = 1;
          flags.altivec  = 1;

Modified: trunk/none/tests/ppc32/jm-int.stdout.exp
==============================================================================
--- trunk/none/tests/ppc32/jm-int.stdout.exp (original)
+++ trunk/none/tests/ppc32/jm-int.stdout.exp Wed May  3 18:28:35 2017
@@ -450,270 +450,6 @@
      subfeo. ffffffff, 000f423f => 000f4240 (40000000 00000000)
      subfeo. ffffffff, ffffffff => 00000000 (20000000 20000000)
 
-PPC integer logical insns with two args:
-         and 00000000, 00000000 => 00000000 (00000000 00000000)
-         and 00000000, 000f423f => 00000000 (00000000 00000000)
-         and 00000000, ffffffff => 00000000 (00000000 00000000)
-         and 000f423f, 00000000 => 00000000 (00000000 00000000)
-         and 000f423f, 000f423f => 000f423f (00000000 00000000)
-         and 000f423f, ffffffff => 000f423f (00000000 00000000)
-         and ffffffff, 00000000 => 00000000 (00000000 00000000)
-         and ffffffff, 000f423f => 000f423f (00000000 00000000)
-         and ffffffff, ffffffff => ffffffff (00000000 00000000)
-
-        andc 00000000, 00000000 => 00000000 (00000000 00000000)
-        andc 00000000, 000f423f => 00000000 (00000000 00000000)
-        andc 00000000, ffffffff => 00000000 (00000000 00000000)
-        andc 000f423f, 00000000 => 000f423f (00000000 00000000)
-        andc 000f423f, 000f423f => 00000000 (00000000 00000000)
-        andc 000f423f, ffffffff => 00000000 (00000000 00000000)
-        andc ffffffff, 00000000 => ffffffff (00000000 00000000)
-        andc ffffffff, 000f423f => fff0bdc0 (00000000 00000000)
-        andc ffffffff, ffffffff => 00000000 (00000000 00000000)
-
-         eqv 00000000, 00000000 => ffffffff (00000000 00000000)
-         eqv 00000000, 000f423f => fff0bdc0 (00000000 00000000)
-         eqv 00000000, ffffffff => 00000000 (00000000 00000000)
-         eqv 000f423f, 00000000 => fff0bdc0 (00000000 00000000)
-         eqv 000f423f, 000f423f => ffffffff (00000000 00000000)
-         eqv 000f423f, ffffffff => 000f423f (00000000 00000000)
-         eqv ffffffff, 00000000 => 00000000 (00000000 00000000)
-         eqv ffffffff, 000f423f => 000f423f (00000000 00000000)
-         eqv ffffffff, ffffffff => ffffffff (00000000 00000000)
-
-        nand 00000000, 00000000 => ffffffff (00000000 00000000)
-        nand 00000000, 000f423f => ffffffff (00000000 00000000)
-        nand 00000000, ffffffff => ffffffff (00000000 00000000)
-        nand 000f423f, 00000000 => ffffffff (00000000 00000000)
-        nand 000f423f, 000f423f => fff0bdc0 (00000000 00000000)
-        nand 000f423f, ffffffff => fff0bdc0 (00000000 00000000)
-        nand ffffffff, 00000000 => ffffffff (00000000 00000000)
-        nand ffffffff, 000f423f => fff0bdc0 (00000000 00000000)
-        nand ffffffff, ffffffff => 00000000 (00000000 00000000)
-
-         nor 00000000, 00000000 => ffffffff (00000000 00000000)
-         nor 00000000, 000f423f => fff0bdc0 (00000000 00000000)
-         nor 00000000, ffffffff => 00000000 (00000000 00000000)
-         nor 000f423f, 00000000 => fff0bdc0 (00000000 00000000)
-         nor 000f423f, 000f423f => fff0bdc0 (00000000 00000000)
-         nor 000f423f, ffffffff => 00000000 (00000000 00000000)
-         nor ffffffff, 00000000 => 00000000 (00000000 00000000)
-         nor ffffffff, 000f423f => 00000000 (00000000 00000000)
-         nor ffffffff, ffffffff => 00000000 (00000000 00000000)
-
-          or 00000000, 00000000 => 00000000 (00000000 00000000)
-          or 00000000, 000f423f => 000f423f (00000000 00000000)
-          or 00000000, ffffffff => ffffffff (00000000 00000000)
-          or 000f423f, 00000000 => 000f423f (00000000 00000000)
-          or 000f423f, 000f423f => 000f423f (00000000 00000000)
-          or 000f423f, ffffffff => ffffffff (00000000 00000000)
-          or ffffffff, 00000000 => ffffffff (00000000 00000000)
-          or ffffffff, 000f423f => ffffffff (00000000 00000000)
-          or ffffffff, ffffffff => ffffffff (00000000 00000000)
-
-         orc 00000000, 00000000 => ffffffff (00000000 00000000)
-         orc 00000000, 000f423f => fff0bdc0 (00000000 00000000)
-         orc 00000000, ffffffff => 00000000 (00000000 00000000)
-         orc 000f423f, 00000000 => ffffffff (00000000 00000000)
-         orc 000f423f, 000f423f => ffffffff (00000000 00000000)
-         orc 000f423f, ffffffff => 000f423f (00000000 00000000)
-         orc ffffffff, 00000000 => ffffffff (00000000 00000000)
-         orc ffffffff, 000f423f => ffffffff (00000000 00000000)
-         orc ffffffff, ffffffff => ffffffff (00000000 00000000)
-
-         xor 00000000, 00000000 => 00000000 (00000000 00000000)
-         xor 00000000, 000f423f => 000f423f (00000000 00000000)
-         xor 00000000, ffffffff => ffffffff (00000000 00000000)
-         xor 000f423f, 00000000 => 000f423f (00000000 00000000)
-         xor 000f423f, 000f423f => 00000000 (00000000 00000000)
-         xor 000f423f, ffffffff => fff0bdc0 (00000000 00000000)
-         xor ffffffff, 00000000 => ffffffff (00000000 00000000)
-         xor ffffffff, 000f423f => fff0bdc0 (00000000 00000000)
-         xor ffffffff, ffffffff => 00000000 (00000000 00000000)
-
-         slw 00000000, 00000000 => 00000000 (00000000 00000000)
-         slw 00000000, 000f423f => 00000000 (00000000 00000000)
-         slw 00000000, ffffffff => 00000000 (00000000 00000000)
-         slw 000f423f, 00000000 => 000f423f (00000000 00000000)
-         slw 000f423f, 000f423f => 00000000 (00000000 00000000)
-         slw 000f423f, ffffffff => 00000000 (00000000 00000000)
-         slw ffffffff, 00000000 => ffffffff (00000000 00000000)
-         slw ffffffff, 000f423f => 00000000 (00000000 00000000)
-         slw ffffffff, ffffffff => 00000000 (00000000 00000000)
-
-        sraw 00000000, 00000000 => 00000000 (00000000 00000000)
-        sraw 00000000, 000f423f => 00000000 (00000000 00000000)
-        sraw 00000000, ffffffff => 00000000 (00000000 00000000)
-        sraw 000f423f, 00000000 => 000f423f (00000000 00000000)
-        sraw 000f423f, 000f423f => 00000000 (00000000 00000000)
-        sraw 000f423f, ffffffff => 00000000 (00000000 00000000)
-        sraw ffffffff, 00000000 => ffffffff (00000000 00000000)
-        sraw ffffffff, 000f423f => ffffffff (00000000 20000000)
-        sraw ffffffff, ffffffff => ffffffff (00000000 20000000)
-
-         srw 00000000, 00000000 => 00000000 (00000000 00000000)
-         srw 00000000, 000f423f => 00000000 (00000000 00000000)
-         srw 00000000, ffffffff => 00000000 (00000000 00000000)
-         srw 000f423f, 00000000 => 000f423f (00000000 00000000)
-         srw 000f423f, 000f423f => 00000000 (00000000 00000000)
-         srw 000f423f, ffffffff => 00000000 (00000000 00000000)
-         srw ffffffff, 00000000 => ffffffff (00000000 00000000)
-         srw ffffffff, 000f423f => 00000000 (00000000 00000000)
-         srw ffffffff, ffffffff => 00000000 (00000000 00000000)
-
-PPC integer logical insns with two args with flags update:
-        and. 00000000, 00000000 => 00000000 (20000000 00000000)
-        and. 00000000, 000f423f => 00000000 (20000000 00000000)
-        and. 00000000, ffffffff => 00000000 (20000000 00000000)
-        and. 000f423f, 00000000 => 00000000 (20000000 00000000)
-        and. 000f423f, 000f423f => 000f423f (40000000 00000000)
-        and. 000f423f, ffffffff => 000f423f (40000000 00000000)
-        and. ffffffff, 00000000 => 00000000 (20000000 00000000)
-        and. ffffffff, 000f423f => 000f423f (40000000 00000000)
-        and. ffffffff, ffffffff => ffffffff (80000000 00000000)
-
-       andc. 00000000, 00000000 => 00000000 (20000000 00000000)
-       andc. 00000000, 000f423f => 00000000 (20000000 00000000)
-       andc. 00000000, ffffffff => 00000000 (20000000 00000000)
-       andc. 000f423f, 00000000 => 000f423f (40000000 00000000)
-       andc. 000f423f, 000f423f => 00000000 (20000000 00000000)
-       andc. 000f423f, ffffffff => 00000000 (20000000 00000000)
-       andc. ffffffff, 00000000 => ffffffff (80000000 00000000)
-       andc. ffffffff, 000f423f => fff0bdc0 (80000000 00000000)
-       andc. ffffffff, ffffffff => 00000000 (20000000 00000000)
-
-        eqv. 00000000, 00000000 => ffffffff (80000000 00000000)
-        eqv. 00000000, 000f423f => fff0bdc0 (80000000 00000000)
-        eqv. 00000000, ffffffff => 00000000 (20000000 00000000)
-        eqv. 000f423f, 00000000 => fff0bdc0 (80000000 00000000)
-        eqv. 000f423f, 000f423f => ffffffff (80000000 00000000)
-        eqv. 000f423f, ffffffff => 000f423f (40000000 00000000)
-        eqv. ffffffff, 00000000 => 00000000 (20000000 00000000)
-        eqv. ffffffff, 000f423f => 000f423f (40000000 00000000)
-        eqv. ffffffff, ffffffff => ffffffff (80000000 00000000)
-
-       nand. 00000000, 00000000 => ffffffff (80000000 00000000)
-       nand. 00000000, 000f423f => ffffffff (80000000 00000000)
-       nand. 00000000, ffffffff => ffffffff (80000000 00000000)
-       nand. 000f423f, 00000000 => ffffffff (80000000 00000000)
-       nand. 000f423f, 000f423f => fff0bdc0 (80000000 00000000)
-       nand. 000f423f, ffffffff => fff0bdc0 (80000000 00000000)
-       nand. ffffffff, 00000000 => ffffffff (80000000 00000000)
-       nand. ffffffff, 000f423f => fff0bdc0 (80000000 00000000)
-       nand. ffffffff, ffffffff => 00000000 (20000000 00000000)
-
-        nor. 00000000, 00000000 => ffffffff (80000000 00000000)
-        nor. 00000000, 000f423f => fff0bdc0 (80000000 00000000)
-        nor. 00000000, ffffffff => 00000000 (20000000 00000000)
-        nor. 000f423f, 00000000 => fff0bdc0 (80000000 00000000)
-        nor. 000f423f, 000f423f => fff0bdc0 (80000000 00000000)
-        nor. 000f423f, ffffffff => 00000000 (20000000 00000000)
-        nor. ffffffff, 00000000 => 00000000 (20000000 00000000)
-        nor. ffffffff, 000f423f => 00000000 (20000000 00000000)
-        nor. ffffffff, ffffffff => 00000000 (20000000 00000000)
-
-         or. 00000000, 00000000 => 00000000 (20000000 00000000)
-         or. 00000000, 000f423f => 000f423f (40000000 00000000)
-         or. 00000000, ffffffff => ffffffff (80000000 00000000)
-         or. 000f423f, 00000000 => 000f423f (40000000 00000000)
-         or. 000f423f, 000f423f => 000f423f (40000000 00000000)
-         or. 000f423f, ffffffff => ffffffff (80000000 00000000)
-         or. ffffffff, 00000000 => ffffffff (80000000 00000000)
-         or. ffffffff, 000f423f => ffffffff (80000000 00000000)
-         or. ffffffff, ffffffff => ffffffff (80000000 00000000)
-
-        orc. 00000000, 00000000 => ffffffff (80000000 00000000)
-        orc. 00000000, 000f423f => fff0bdc0 (80000000 00000000)
-        orc. 00000000, ffffffff => 00000000 (20000000 00000000)
-        orc. 000f423f, 00000000 => ffffffff (80000000 00000000)
-        orc. 000f423f, 000f423f => ffffffff (80000000 00000000)
-        orc. 000f423f, ffffffff => 000f423f (40000000 00000000)
-        orc. ffffffff, 00000000 => ffffffff (80000000 00000000)
-        orc. ffffffff, 000f423f => ffffffff (80000000 00000000)
-        orc. ffffffff, ffffffff => ffffffff (80000000 00000000)
-
-        xor. 00000000, 00000000 => 00000000 (20000000 00000000)
-        xor. 00000000, 000f423f => 000f423f (40000000 00000000)
-        xor. 00000000, ffffffff => ffffffff (80000000 00000000)
-        xor. 000f423f, 00000000 => 000f423f (40000000 00000000)
-        xor. 000f423f, 000f423f => 00000000 (20000000 00000000)
-        xor. 000f423f, ffffffff => fff0bdc0 (80000000 00000000)
-        xor. ffffffff, 00000000 => ffffffff (80000000 00000000)
-        xor. ffffffff, 000f423f => fff0bdc0 (80000000 00000000)
-        xor. ffffffff, ffffffff => 00000000 (20000000 00000000)
-
-        slw. 00000000, 00000000 => 00000000 (20000000 00000000)
-        slw. 00000000, 000f423f => 00000000 (20000000 00000000)
-        slw. 00000000, ffffffff => 00000000 (20000000 00000000)
-        slw. 000f423f, 00000000 => 000f423f (40000000 00000000)
-        slw. 000f423f, 000f423f => 00000000 (20000000 00000000)
-        slw. 000f423f, ffffffff => 00000000 (20000000 00000000)
-        slw. ffffffff, 00000000 => ffffffff (80000000 00000000)
-        slw. ffffffff, 000f423f => 00000000 (20000000 00000000)
-        slw. ffffffff, ffffffff => 00000000 (20000000 00000000)
-
-       sraw. 00000000, 00000000 => 00000000 (20000000 00000000)
-       sraw. 00000000, 000f423f => 00000000 (20000000 00000000)
-       sraw. 00000000, ffffffff => 00000000 (20000000 00000000)
-       sraw. 000f423f, 00000000 => 000f423f (40000000 00000000)
-       sraw. 000f423f, 000f423f => 00000000 (20000000 00000000)
-       sraw. 000f423f, ffffffff => 00000000 (20000000 00000000)
-       sraw. ffffffff, 00000000 => ffffffff (80000000 00000000)
-       sraw. ffffffff, 000f423f => ffffffff (80000000 20000000)
-       sraw. ffffffff, ffffffff => ffffffff (80000000 20000000)
-
-        srw. 00000000, 00000000 => 00000000 (20000000 00000000)
-        srw. 00000000, 000f423f => 00000000 (20000000 00000000)
-        srw. 00000000, ffffffff => 00000000 (20000000 00000000)
-        srw. 000f423f, 00000000 => 000f423f (40000000 00000000)
-        srw. 000f423f, 000f423f => 00000000 (20000000 00000000)
-        srw. 000f423f, ffffffff => 00000000 (20000000 00000000)
-        srw. ffffffff, 00000000 => ffffffff (80000000 00000000)
-        srw. ffffffff, 000f423f => 00000000 (20000000 00000000)
-        srw. ffffffff, ffffffff => 00000000 (20000000 00000000)
-
-PPC integer compare insns (two args):
-        cmpw 00000000, 00000000 => 00000000 (00200000 00000000)
-        cmpw 00000000, 000f423f => 00000000 (00800000 00000000)
-        cmpw 00000000, ffffffff => 00000000 (00400000 00000000)
-        cmpw 000f423f, 00000000 => 00000000 (00400000 00000000)
-        cmpw 000f423f, 000f423f => 00000000 (00200000 00000000)
-        cmpw 000f423f, ffffffff => 00000000 (00400000 00000000)
-        cmpw ffffffff, 00000000 => 00000000 (00800000 00000000)
-        cmpw ffffffff, 000f423f => 00000000 (00800000 00000000)
-        cmpw ffffffff, ffffffff => 00000000 (00200000 00000000)
-
-       cmplw 00000000, 00000000 => 00000000 (00200000 00000000)
-       cmplw 00000000, 000f423f => 00000000 (00800000 00000000)
-       cmplw 00000000, ffffffff => 00000000 (00800000 00000000)
-       cmplw 000f423f, 00000000 => 00000000 (00400000 00000000)
-       cmplw 000f423f, 000f423f => 00000000 (00200000 00000000)
-       cmplw 000f423f, ffffffff => 00000000 (00800000 00000000)
-       cmplw ffffffff, 00000000 => 00000000 (00400000 00000000)
-       cmplw ffffffff, 000f423f => 00000000 (00400000 00000000)
-       cmplw ffffffff, ffffffff => 00000000 (00200000 00000000)
-
-PPC integer compare with immediate insns (two args):
-       cmpwi 00000000, 00000000 => 00000000 (00200000 00000000)
-       cmpwi 00000000, 000003e7 => 00000000 (00800000 00000000)
-       cmpwi 00000000, 0000ffff => 00000000 (00400000 00000000)
-       cmpwi 000f423f, 00000000 => 00000000 (00400000 00000000)
-       cmpwi 000f423f, 000003e7 => 00000000 (00400000 00000000)
-       cmpwi 000f423f, 0000ffff => 00000000 (00400000 00000000)
-       cmpwi ffffffff, 00000000 => 00000000 (00800000 00000000)
-       cmpwi ffffffff, 000003e7 => 00000000 (00800000 00000000)
-       cmpwi ffffffff, 0000ffff => 00000000 (00200000 00000000)
-
-      cmplwi 00000000, 00000000 => 00000000 (00200000 00000000)
-      cmplwi 00000000, 000003e7 => 00000000 (00800000 00000000)
-      cmplwi 00000000, 0000ffff => 00000000 (00800000 00000000)
-      cmplwi 000f423f, 00000000 => 00000000 (00400000 00000000)
-      cmplwi 000f423f, 000003e7 => 00000000 (00400000 00000000)
-      cmplwi 000f423f, 0000ffff => 00000000 (00400000 00000000)
-      cmplwi ffffffff, 00000000 => 00000000 (00400000 00000000)
-      cmplwi ffffffff, 000003e7 => 00000000 (00400000 00000000)
-      cmplwi ffffffff, 0000ffff => 00000000 (00400000 00000000)
-
 PPC integer arith insns
     with one register + one 16 bits immediate args:
         addi 00000000, 00000000 => 00000000 (00000000 00000000)
@@ -778,151 +514,6 @@
       addic. ffffffff, 000003e7 => 000003e6 (40000000 20000000)
       addic. ffffffff, 0000ffff => fffffffe (80000000 20000000)
 
-PPC integer logical insns
-    with one register + one 16 bits immediate args:
-         ori 00000000, 00000000 => 00000000 (00000000 00000000)
-         ori 00000000, 000003e7 => 000003e7 (00000000 00000000)
-         ori 00000000, 0000ffff => 0000ffff (00000000 00000000)
-         ori 000f423f, 00000000 => 000f423f (00000000 00000000)
-         ori 000f423f, 000003e7 => 000f43ff (00000000 00000000)
-         ori 000f423f, 0000ffff => 000fffff (00000000 00000000)
-         ori ffffffff, 00000000 => ffffffff (00000000 00000000)
-         ori ffffffff, 000003e7 => ffffffff (00000000 00000000)
-         ori ffffffff, 0000ffff => ffffffff (00000000 00000000)
-
-        oris 00000000, 00000000 => 00000000 (00000000 00000000)
-        oris 00000000, 000003e7 => 03e70000 (00000000 00000000)
-        oris 00000000, 0000ffff => ffff0000 (00000000 00000000)
-        oris 000f423f, 00000000 => 000f423f (00000000 00000000)
-        oris 000f423f, 000003e7 => 03ef423f (00000000 00000000)
-        oris 000f423f, 0000ffff => ffff423f (00000000 00000000)
-        oris ffffffff, 00000000 => ffffffff (00000000 00000000)
-        oris ffffffff, 000003e7 => ffffffff (00000000 00000000)
-        oris ffffffff, 0000ffff => ffffffff (00000000 00000000)
-
-        xori 00000000, 00000000 => 00000000 (00000000 00000000)
-        xori 00000000, 000003e7 => 000003e7 (00000000 00000000)
-        xori 00000000, 0000ffff => 0000ffff (00000000 00000000)
-        xori 000f423f, 00000000 => 000f423f (00000000 00000000)
-        xori 000f423f, 000003e7 => 000f41d8 (00000000 00000000)
-        xori 000f423f, 0000ffff => 000fbdc0 (00000000 00000000)
-        xori ffffffff, 00000000 => ffffffff (00000000 00000000)
-        xori ffffffff, 000003e7 => fffffc18 (00000000 00000000)
-        xori ffffffff, 0000ffff => ffff0000 (00000000 00000000)
-
-       xoris 00000000, 00000000 => 00000000 (00000000 00000000)
-       xoris 00000000, 000003e7 => 03e70000 (00000000 00000000)
-       xoris 00000000, 0000ffff => ffff0000 (00000000 00000000)
-       xoris 000f423f, 00000000 => 000f423f (00000000 00000000)
-       xoris 000f423f, 000003e7 => 03e8423f (00000000 00000000)
-       xoris 000f423f, 0000ffff => fff0423f (00000000 00000000)
-       xoris ffffffff, 00000000 => ffffffff (00000000 00000000)
-       xoris ffffffff, 000003e7 => fc18ffff (00000000 00000000)
-       xoris ffffffff, 0000ffff => 0000ffff (00000000 00000000)
-
-PPC integer logical insns
-    with one register + one 16 bits immediate args with flags update:
-       andi. 00000000, 00000000 => 00000000 (20000000 00000000)
-       andi. 00000000, 000003e7 => 00000000 (20000000 00000000)
-       andi. 00000000, 0000ffff => 00000000 (20000000 00000000)
-       andi. 000f423f, 00000000 => 00000000 (20000000 00000000)
-       andi. 000f423f, 000003e7 => 00000227 (40000000 00000000)
-       andi. 000f423f, 0000ffff => 0000423f (40000000 00000000)
-       andi. ffffffff, 00000000 => 00000000 (20000000 00000000)
-       andi. ffffffff, 000003e7 => 000003e7 (40000000 00000000)
-       andi. ffffffff, 0000ffff => 0000ffff (40000000 00000000)
-
-      andis. 00000000, 00000000 => 00000000 (20000000 00000000)
-      andis. 00000000, 000003e7 => 00000000 (20000000 00000000)
-      andis. 00000000, 0000ffff => 00000000 (20000000 00000000)
-      andis. 000f423f, 00000000 => 00000000 (20000000 00000000)
-      andis. 000f423f, 000003e7 => 00070000 (40000000 00000000)
-      andis. 000f423f, 0000ffff => 000f0000 (40000000 00000000)
-      andis. ffffffff, 00000000 => 00000000 (20000000 00000000)
-      andis. ffffffff, 000003e7 => 03e70000 (40000000 00000000)
-      andis. ffffffff, 0000ffff => ffff0000 (80000000 00000000)
-
-PPC condition register logical insns - two operands:
-       crand 00000000, 00000000 => ffff0000 (00000000 00000000)
-       crand 00000000, 000f423f => ffff0000 (00000000 00000000)
-       crand 00000000, ffffffff => ffff0000 (00000000 00000000)
-       crand 000f423f, 00000000 => ffff0000 (00000000 00000000)
-       crand 000f423f, 000f423f => ffff0000 (00000000 00000000)
-       crand 000f423f, ffffffff => ffff0000 (00000000 00000000)
-       crand ffffffff, 00000000 => ffff0000 (00000000 00000000)
-       crand ffffffff, 000f423f => ffff0000 (00000000 00000000)
-       crand ffffffff, ffffffff => ffff0000 (00000000 00000000)
-
-      crandc 00000000, 00000000 => ffff0000 (00000000 00000000)
-      crandc 00000000, 000f423f => ffff0000 (00000000 00000000)
-      crandc 00000000, ffffffff => ffff0000 (00000000 00000000)
-      crandc 000f423f, 00000000 => ffff0000 (00000000 00000000)
-      crandc 000f423f, 000f423f => ffff0000 (00000000 00000000)
-      crandc 000f423f, ffffffff => ffff0000 (00000000 00000000)
-      crandc ffffffff, 00000000 => ffff0000 (00000000 00000000)
-      crandc ffffffff, 000f423f => ffff0000 (00000000 00000000)
-      crandc ffffffff, ffffffff => ffff0000 (00000000 00000000)
-
-       creqv 00000000, 00000000 => ffff0000 (00004000 00000000)
-       creqv 00000000, 000f423f => ffff0000 (00004000 00000000)
-       creqv 00000000, ffffffff => ffff0000 (00004000 00000000)
-       creqv 000f423f, 00000000 => ffff0000 (00004000 00000000)
-       creqv 000f423f, 000f423f => ffff0000 (00004000 00000000)
-       creqv 000f423f, ffffffff => ffff0000 (00004000 00000000)
-       creqv ffffffff, 00000000 => ffff0000 (00004000 00000000)
-       creqv ffffffff, 000f423f => ffff0000 (00004000 00000000)
-       creqv ffffffff, ffffffff => ffff0000 (00004000 00000000)
-
-      crnand 00000000, 00000000 => ffff0000 (00004000 00000000)
-      crnand 00000000, 000f423f => ffff0000 (00004000 00000000)
-      crnand 00000000, ffffffff => ffff0000 (00004000 00000000)
-      crnand 000f423f, 00000000 => ffff0000 (00004000 00000000)
-      crnand 000f423f, 000f423f => ffff0000 (00004000 00000000)
-      crnand 000f423f, ffffffff => ffff0000 (00004000 00000000)
-      crnand ffffffff, 00000000 => ffff0000 (00004000 00000000)
-      crnand ffffffff, 000f423f => ffff0000 (00004000 00000000)
-      crnand ffffffff, ffffffff => ffff0000 (00004000 00000000)
-
-       crnor 00000000, 00000000 => ffff0000 (00004000 00000000)
-       crnor 00000000, 000f423f => ffff0000 (00004000 00000000)
-       crnor 00000000, ffffffff => ffff0000 (00004000 00000000)
-       crnor 000f423f, 00000000 => ffff0000 (00004000 00000000)
-       crnor 000f423f, 000f423f => ffff0000 (00004000 00000000)
-       crnor 000f423f, ffffffff => ffff0000 (00004000 00000000)
-       crnor ffffffff, 00000000 => ffff0000 (00004000 00000000)
-       crnor ffffffff, 000f423f => ffff0000 (00004000 00000000)
-       crnor ffffffff, ffffffff => ffff0000 (00004000 00000000)
-
-        cror 00000000, 00000000 => ffff0000 (00000000 00000000)
-        cror 00000000, 000f423f => ffff0000 (00000000 00000000)
-        cror 00000000, ffffffff => ffff0000 (00000000 00000000)
-        cror 000f423f, 00000000 => ffff0000 (00000000 00000000)
-        cror 000f423f, 000f423f => ffff0000 (00000000 00000000)
-        cror 000f423f, ffffffff => ffff0000 (00000000 00000000)
-        cror ffffffff, 00000000 => ffff0000 (00000000 00000000)
-        cror ffffffff, 000f423f => ffff0000 (00000000 00000000)
-        cror ffffffff, ffffffff => ffff0000 (00000000 00000000)
-
-       crorc 00000000, 00000000 => ffff0000 (00004000 00000000)
-       crorc 00000000, 000f423f => ffff0000 (00004000 00000000)
-       crorc 00000000, ffffffff => ffff0000 (00004000 00000000)
-       crorc 000f423f, 00000000 => ffff0000 (00004000 00000000)
-       crorc 000f423f, 000f423f => ffff0000 (00004000 00000000)
-       crorc 000f423f, ffffffff => ffff0000 (00004000 00000000)
-       crorc ffffffff, 00000000 => ffff0000 (00004000 00000000)
-       crorc ffffffff, 000f423f => ffff0000 (00004000 00000000)
-       crorc ffffffff, ffffffff => ffff0000 (00004000 00000000)
-
-       crxor 00000000, 00000000 => ffff0000 (00000000 00000000)
-       crxor 00000000, 000f423f => ffff0000 (00000000 00000000)
-       crxor 00000000, ffffffff => ffff0000 (00000000 00000000)
-       crxor 000f423f, 00000000 => ffff0000 (00000000 00000000)
-       crxor 000f423f, 000f423f => ffff0000 (00000000 00000000)
-       crxor 000f423f, ffffffff => ffff0000 (00000000 00000000)
-       crxor ffffffff, 00000000 => ffff0000 (00000000 00000000)
-       crxor ffffffff, 000f423f => ffff0000 (00000000 00000000)
-       crxor ffffffff, ffffffff => ffff0000 (00000000 00000000)
-
 PPC integer arith insns with one arg and carry:
        addme 00000000 => ffffffff (00000000 00000000)
        addme 000f423f => 000f423e (00000000 20000000)
@@ -1037,568 +628,9 @@
     subfzeo. 000f423f => fff0bdc1 (80000000 00000000)
     subfzeo. ffffffff => 00000001 (40000000 00000000)
 
-PPC integer logical insns with one arg:
-      cntlzw 00000000 => 00000020 (00000000 00000000)
-      cntlzw 000f423f => 0000000c (00000000 00000000)
-      cntlzw ffffffff => 00000000 (00000000 00000000)
-
-       extsb 00000000 => 00000000 (00000000 00000000)
-       extsb 000f423f => 0000003f (00000000 00000000)
-       extsb ffffffff => ffffffff (00000000 00000000)
-
-       extsh 00000000 => 00000000 (00000000 00000000)
-       extsh 000f423f => 0000423f (00000000 00000000)
-       extsh ffffffff => ffffffff (00000000 00000000)
-
-         neg 00000000 => 00000000 (00000000 00000000)
-         neg 000f423f => fff0bdc1 (00000000 00000000)
-         neg ffffffff => 00000001 (00000000 00000000)
-
-        nego 00000000 => 00000000 (00000000 00000000)
-        nego 000f423f => fff0bdc1 (00000000 00000000)
-        nego ffffffff => 00000001 (00000000 00000000)
-
-PPC integer logical insns with one arg with flags update:
-     cntlzw. 00000000 => 00000020 (40000000 00000000)
-     cntlzw. 000f423f => 0000000c (40000000 00000000)
-     cntlzw. ffffffff => 00000000 (20000000 00000000)
-
-      extsb. 00000000 => 00000000 (20000000 00000000)
-      extsb. 000f423f => 0000003f (40000000 00000000)
-      extsb. ffffffff => ffffffff (80000000 00000000)
-
-      extsh. 00000000 => 00000000 (20000000 00000000)
-      extsh. 000f423f => 0000423f (40000000 00000000)
-      extsh. ffffffff => ffffffff (80000000 00000000)
-
-        neg. 00000000 => 00000000 (20000000 00000000)
-        neg. 000f423f => fff0bdc1 (80000000 00000000)
-        neg. ffffffff => 00000001 (40000000 00000000)
-
-       nego. 00000000 => 00000000 (20000000 00000000)
-       nego. 000f423f => fff0bdc1 (80000000 00000000)
-       nego. ffffffff => 00000001 (40000000 00000000)
-
-PPC logical insns with special forms:
-      rlwimi 00000000,  0,  0,  0 => 00000000 (00000000 00000000)
-      rlwimi 00000000,  0,  0, 31 => 00000000 (00000000 00000000)
-      rlwimi 00000000,  0, 31,  0 => 00000000 (00000000 00000000)
-      rlwimi 00000000,  0, 31, 31 => 00000000 (00000000 00000000)
-      rlwimi 00000000, 31,  0,  0 => 00000000 (00000000 00000000)
-      rlwimi 00000000, 31,  0, 31 => 00000000 (00000000 00000000)
-      rlwimi 00000000, 31, 31,  0 => 00000000 (00000000 00000000)
-      rlwimi 00000000, 31, 31, 31 => 00000000 (00000000 00000000)
-      rlwimi 000f423f,  0,  0,  0 => 00000000 (00000000 00000000)
-      rlwimi 000f423f,  0,  0, 31 => 000f423f (00000000 00000000)
-      rlwimi 000f423f,  0, 31,  0 => 000f423f (00000000 00000000)
-      rlwimi 000f423f,  0, 31, 31 => 000f423f (00000000 00000000)
-      rlwimi 000f423f, 31,  0,  0 => 800f423f (00000000 00000000)
-      rlwimi 000f423f, 31,  0, 31 => 8007a11f (00000000 00000000)
-      rlwimi 000f423f, 31, 31,  0 => 8007a11f (00000000 00000000)
-      rlwimi 000f423f, 31, 31, 31 => 8007a11f (00000000 00000000)
-      rlwimi ffffffff,  0,  0,  0 => 8007a11f (00000000 00000000)
-      rlwimi ffffffff,  0,  0, 31 => ffffffff (00000000 00000000)
-      rlwimi ffffffff,  0, 31,  0 => ffffffff (00000000 00000000)
-      rlwimi ffffffff,  0, 31, 31 => ffffffff (00000000 00000000)
-      rlwimi ffffffff, 31,  0,  0 => ffffffff (00000000 00000000)
-      rlwimi ffffffff, 31,  0, 31 => ffffffff (00000000 00000000)
-      rlwimi ffffffff, 31, 31,  0 => ffffffff (00000000 00000000)
-      rlwimi ffffffff, 31, 31, 31 => ffffffff (00000000 00000000)
-
-      rlwinm 00000000,  0,  0,  0 => 00000000 (00000000 00000000)
-      rlwinm 00000000,  0,  0, 31 => 00000000 (00000000 00000000)
-      rlwinm 00000000,  0, 31,  0 => 00000000 (00000000 00000000)
-      rlwinm 00000000,  0, 31, 31 => 00000000 (00000000 00000000)
-      rlwinm 00000000, 31,  0,  0 => 00000000 (00000000 00000000)
-      rlwinm 00000000, 31,  0, 31 => 00000000 (00000000 00000000)
-      rlwinm 00000000, 31, 31,  0 => 00000000 (00000000 00000000)
-      rlwinm 00000000, 31, 31, 31 => 00000000 (00000000 00000000)
-      rlwinm 000f423f,  0,  0,  0 => 00000000 (00000000 00000000)
-      rlwinm 000f423f,  0,  0, 31 => 000f423f (00000000 00000000)
-      rlwinm 000f423f,  0, 31,  0 => 00000001 (00000000 00000000)
-      rlwinm 000f423f,  0, 31, 31 => 00000001 (00000000 00000000)
-      rlwinm 000f423f, 31,  0,  0 => 80000000 (00000000 00000000)
-      rlwinm 000f423f, 31,  0, 31 => 8007a11f (00000000 00000000)
-      rlwinm 000f423f, 31, 31,  0 => 80000001 (00000000 00000000)
-      rlwinm 000f423f, 31, 31, 31 => 00000001 (00000000 00000000)
-      rlwinm ffffffff,  0,  0,  0 => 80000000 (00000000 00000000)
-      rlwinm ffffffff,  0,  0, 31 => ffffffff (00000000 00000000)
-      rlwinm ffffffff,  0, 31,  0 => 80000001 (00000000 00000000)
-      rlwinm ffffffff,  0, 31, 31 => 00000001 (00000000 00000000)
-      rlwinm ffffffff, 31,  0,  0 => 80000000 (00000000 00000000)
-      rlwinm ffffffff, 31,  0, 31 => ffffffff (00000000 00000000)
-      rlwinm ffffffff, 31, 31,  0 => 80000001 (00000000 00000000)
-      rlwinm ffffffff, 31, 31, 31 => 00000001 (00000000 00000000)
-
-       rlwnm 00000000, 00000000,  0,  0 => 00000000 (00000000 00000000)
-       rlwnm 00000000, 00000000,  0, 31 => 00000000 (00000000 00000000)
-       rlwnm 00000000, 00000000, 31,  0 => 00000000 (00000000 00000000)
-       rlwnm 00000000, 00000000, 31, 31 => 00000000 (00000000 00000000)
-       rlwnm 00000000, 000f423f,  0,  0 => 00000000 (00000000 00000000)
-       rlwnm 00000000, 000f423f,  0, 31 => 00000000 (00000000 00000000)
-       rlwnm 00000000, 000f423f, 31,  0 => 00000000 (00000000 00000000)
-       rlwnm 00000000, 000f423f, 31, 31 => 00000000 (00000000 00000000)
-       rlwnm 00000000, ffffffff,  0,  0 => 00000000 (00000000 00000000)
-       rlwnm 00000000, ffffffff,  0, 31 => 00000000 (00000000 00000000)
-       rlwnm 00000000, ffffffff, 31,  0 => 00000000 (00000000 00000000)
-       rlwnm 00000000, ffffffff, 31, 31 => 00000000 (00000000 00000000)
-       rlwnm 000f423f, 00000000,  0,  0 => 00000000 (00000000 00000000)
-       rlwnm 000f423f, 00000000,  0, 31 => 000f423f (00000000 00000000)
-       rlwnm 000f423f, 00000000, 31,  0 => 00000001 (00000000 00000000)
-       rlwnm 000f423f, 00000000, 31, 31 => 00000001 (00000000 00000000)
-       rlwnm 000f423f, 000f423f,  0,  0 => 80000000 (00000000 00000000)
-       rlwnm 000f423f, 000f423f,  0, 31 => 8007a11f (00000000 00000000)
-       rlwnm 000f423f, 000f423f, 31,  0 => 80000001 (00000000 00000000)
-       rlwnm 000f423f, 000f423f, 31, 31 => 00000001 (00000000 00000000)
-       rlwnm 000f423f, ffffffff,  0,  0 => 80000000 (00000000 00000000)
-       rlwnm 000f423f, ffffffff,  0, 31 => 8007a11f (00000000 00000000)
-       rlwnm 000f423f, ffffffff, 31,  0 => 80000001 (00000000 00000000)
-       rlwnm 000f423f, ffffffff, 31, 31 => 00000001 (00000000 00000000)
-       rlwnm ffffffff, 00000000,  0,  0 => 80000000 (00000000 00000000)
-       rlwnm ffffffff, 00000000,  0, 31 => ffffffff (00000000 00000000)
-       rlwnm ffffffff, 00000000, 31,  0 => 80000001 (00000000 00000000)
-       rlwnm ffffffff, 00000000, 31, 31 => 00000001 (00000000 00000000)
-       rlwnm ffffffff, 000f423f,  0,  0 => 80000000 (00000000 00000000)
-       rlwnm ffffffff, 000f423f,  0, 31 => ffffffff (00000000 00000000)
-       rlwnm ffffffff, 000f423f, 31,  0 => 80000001 (00000000 00000000)
-       rlwnm ffffffff, 000f423f, 31, 31 => 00000001 (00000000 00000000)
-       rlwnm ffffffff, ffffffff,  0,  0 => 80000000 (00000000 00000000)
-       rlwnm ffffffff, ffffffff,  0, 31 => ffffffff (00000000 00000000)
-       rlwnm ffffffff, ffffffff, 31,  0 => 80000001 (00000000 00000000)
-       rlwnm ffffffff, ffffffff, 31, 31 => 00000001 (00000000 00000000)
-
-       srawi 00000000,  0 => 00000000 (00000000 00000000)
-       srawi 00000000, 31 => 00000000 (00000000 00000000)
-       srawi 000f423f,  0 => 000f423f (00000000 00000000)
-       srawi 000f423f, 31 => 00000000 (00000000 00000000)
-       srawi ffffffff,  0 => ffffffff (00000000 00000000)
-       srawi ffffffff, 31 => ffffffff (00000000 20000000)
-
-        mfcr (00000000) => 00000000 (00000000 00000000)
-        mfcr (000f423f) => 000f423f (000f423f 00000000)
-        mfcr (ffffffff) => ffffffff (ffffffff 00000000)
-
-       mfspr 1 (00000000) -> mtxer -> mfxer => 00000000
-       mfspr 1 (000f423f) -> mtxer -> mfxer => 0000003f
-       mfspr 1 (ffffffff) -> mtxer -> mfxer => e000007f
-       mfspr 8 (00000000) ->  mtlr ->  mflr => 00000000
-       mfspr 8 (000f423f) ->  mtlr ->  mflr => 000f423f
-       mfspr 8 (ffffffff) ->  mtlr ->  mflr => ffffffff
-       mfspr 9 (00000000) -> mtctr -> mfctr => 00000000
-       mfspr 9 (000f423f) -> mtctr -> mfctr => 000f423f
-       mfspr 9 (ffffffff) -> mtctr -> mfctr => ffffffff
-
-
-PPC logical insns with special forms with flags update:
-     rlwimi. 00000000,  0,  0,  0 => 00000000 (20000000 00000000)
-     rlwimi. 00000000,  0,  0, 31 => 00000000 (20000000 00000000)
-     rlwimi. 00000000,  0, 31,  0 => 00000000 (20000000 00000000)
-     rlwimi. 00000000,  0, 31, 31 => 00000000 (20000000 00000000)
-     rlwimi. 00000000, 31,  0,  0 => 00000000 (20000000 00000000)
-     rlwimi. 00000000, 31,  0, 31 => 00000000 (20000000 00000000)
-     rlwimi. 00000000, 31, 31,  0 => 00000000 (20000000 00000000)
-     rlwimi. 00000000, 31, 31, 31 => 00000000 (20000000 00000000)
-     rlwimi. 000f423f,  0,  0,  0 => 00000000 (20000000 00000000)
-     rlwimi. 000f423f,  0,  0, 31 => 000f423f (40000000 00000000)
-     rlwimi. 000f423f,  0, 31,  0 => 000f423f (40000000 00000000)
-     rlwimi. 000f423f,  0, 31, 31 => 000f423f (40000000 00000000)
-     rlwimi. 000f423f, 31,  0,  0 => 800f423f (80000000 00000000)
-     rlwimi. 000f423f, 31,  0, 31 => 8007a11f (80000000 00000000)
-     rlwimi. 000f423f, 31, 31,  0 => 8007a11f (80000000 00000000)
-     rlwimi. 000f423f, 31, 31, 31 => 8007a11f (80000000 00000000)
-     rlwimi. ffffffff,  0,  0,  0 => 8007a11f (80000000 00000000)
-     rlwimi. ffffffff,  0,  0, 31 => ffffffff (80000000 00000000)
-     rlwimi. ffffffff,  0, 31,  0 => ffffffff (80000000 00000000)
-     rlwimi. ffffffff,  0, 31, 31 => ffffffff (80000000 00000000)
-     rlwimi. ffffffff, 31,  0,  0 => ffffffff (80000000 00000000)
-     rlwimi. ffffffff, 31,  0, 31 => ffffffff (80000000 00000000)
-     rlwimi. ffffffff, 31, 31,  0 => ffffffff (80000000 00000000)
-     rlwimi. ffffffff, 31, 31, 31 => ffffffff (80000000 00000000)
-
-     rlwinm. 00000000,  0,  0,  0 => 00000000 (20000000 00000000)
-     rlwinm. 00000000,  0,  0, 31 => 00000000 (20000000 00000000)
-     rlwinm. 00000000,  0, 31,  0 => 00000000 (20000000 00000000)
-     rlwinm. 00000000,  0, 31, 31 => 00000000 (20000000 00000000)
-     rlwinm. 00000000, 31,  0,  0 => 00000000 (20000000 00000000)
-     rlwinm. 00000000, 31,  0, 31 => 00000000 (20000000 00000000)
-     rlwinm. 00000000, 31, 31,  0 => 00000000 (20000000 00000000)
-     rlwinm. 00000000, 31, 31, 31 => 00000000 (20000000 00000000)
-     rlwinm. 000f423f,  0,  0,  0 => 00000000 (20000000 00000000)
-     rlwinm. 000f423f,  0,  0, 31 => 000f423f (40000000 00000000)
-     rlwinm. 000f423f,  0, 31,  0 => 00000001 (40000000 00000000)
-     rlwinm. 000f423f,  0, 31, 31 => 00000001 (40000000 00000000)
-     rlwinm. 000f423f, 31,  0,  0 => 80000000 (80000000 00000000)
-     rlwinm. 000f423f, 31,  0, 31 => 8007a11f (80000000 00000000)
-     rlwinm. 000f423f, 31, 31,  0 => 80000001 (80000000 00000000)
-     rlwinm. 000f423f, 31, 31, 31 => 00000001 (40000000 00000000)
-     rlwinm. ffffffff,  0,  0,  0 => 80000000 (80000000 00000000)
-     rlwinm. ffffffff,  0,  0, 31 => ffffffff (80000000 00000000)
-     rlwinm. ffffffff,  0, 31,  0 => 80000001 (80000000 00000000)
-     rlwinm. ffffffff,  0, 31, 31 => 00000001 (40000000 00000000)
-     rlwinm. ffffffff, 31,  0,  0 => 80000000 (80000000 00000000)
-     rlwinm. ffffffff, 31,  0, 31 => ffffffff (80000000 00000000)
-     rlwinm. ffffffff, 31, 31,  0 => 80000001 (80000000 00000000)
-     rlwinm. ffffffff, 31, 31, 31 => 00000001 (40000000 00000000)
-
-      rlwnm. 00000000, 00000000,  0,  0 => 00000000 (20000000 00000000)
-      rlwnm. 00000000, 00000000,  0, 31 => 00000000 (20000000 00000000)
-      rlwnm. 00000000, 00000000, 31,  0 => 00000000 (20000000 00000000)
-      rlwnm. 00000000, 00000000, 31, 31 => 00000000 (20000000 00000000)
-      rlwnm. 00000000, 000f423f,  0,  0 => 00000000 (20000000 00000000)
-      rlwnm. 00000000, 000f423f,  0, 31 => 00000000 (20000000 00000000)
-      rlwnm. 00000000, 000f423f, 31,  0 => 00000000 (20000000 00000000)
-      rlwnm. 00000000, 000f423f, 31, 31 => 00000000 (20000000 00000000)
-      rlwnm. 00000000, ffffffff,  0,  0 => 00000000 (20000000 00000000)
-      rlwnm. 00000000, ffffffff,  0, 31 => 00000000 (20000000 00000000)
-      rlwnm. 00000000, ffffffff, 31,  0 => 00000000 (20000000 00000000)
-      rlwnm. 00000000, ffffffff, 31, 31 => 00000000 (20000000 00000000)
-      rlwnm. 000f423f, 00000000,  0,  0 => 00000000 (20000000 00000000)
-      rlwnm. 000f423f, 00000000,  0, 31 => 000f423f (40000000 00000000)
-      rlwnm. 000f423f, 00000000, 31,  0 => 00000001 (40000000 00000000)
-      rlwnm. 000f423f, 00000000, 31, 31 => 00000001 (40000000 00000000)
-      rlwnm. 000f423f, 000f423f,  0,  0 => 80000000 (80000000 00000000)
-      rlwnm. 000f423f, 000f423f,  0, 31 => 8007a11f (80000000 00000000)
-      rlwnm. 000f423f, 000f423f, 31,  0 => 80000001 (80000000 00000000)
-      rlwnm. 000f423f, 000f423f, 31, 31 => 00000001 (40000000 00000000)
-      rlwnm. 000f423f, ffffffff,  0,  0 => 80000000 (80000000 00000000)
-      rlwnm. 000f423f, ffffffff,  0, 31 => 8007a11f (80000000 00000000)
-      rlwnm. 000f423f, ffffffff, 31,  0 => 80000001 (80000000 00000000)
-      rlwnm. 000f423f, ffffffff, 31, 31 => 00000001 (40000000 00000000)
-      rlwnm. ffffffff, 00000000,  0,  0 => 80000000 (80000000 00000000)
-      rlwnm. ffffffff, 00000000,  0, 31 => ffffffff (80000000 00000000)
-      rlwnm. ffffffff, 00000000, 31,  0 => 80000001 (80000000 00000000)
-      rlwnm. ffffffff, 00000000, 31, 31 => 00000001 (40000000 00000000)
-      rlwnm. ffffffff, 000f423f,  0,  0 => 80000000 (80000000 00000000)
-      rlwnm. ffffffff, 000f423f,  0, 31 => ffffffff (80000000 00000000)
-      rlwnm. ffffffff, 000f423f, 31,  0 => 80000001 (80000000 00000000)
-      rlwnm. ffffffff, 000f423f, 31, 31 => 00000001 (40000000 00000000)
-      rlwnm. ffffffff, ffffffff,  0,  0 => 80000000 (80000000 00000000)
-      rlwnm. ffffffff, ffffffff,  0, 31 => ffffffff (80000000 00000000)
-      rlwnm. ffffffff, ffffffff, 31,  0 => 80000001 (80000000 00000000)
-      rlwnm. ffffffff, ffffffff, 31, 31 => 00000001 (40000000 00000000)
-
-      srawi. 00000000,  0 => 00000000 (20000000 00000000)
-      srawi. 00000000, 31 => 00000000 (20000000 00000000)
-      srawi. 000f423f,  0 => 000f423f (40000000 00000000)
-      srawi. 000f423f, 31 => 00000000 (20000000 00000000)
-      srawi. ffffffff,  0 => ffffffff (80000000 00000000)
-      srawi. ffffffff, 31 => ffffffff (80000000 20000000)
-
-        mcrf 0, 0 (00000000) => (00000000 00000000)
-        mcrf 0, 7 (00000000) => (00000000 00000000)
-        mcrf 7, 0 (00000000) => (00000000 00000000)
-        mcrf 7, 7 (00000000) => (00000000 00000000)
-        mcrf 0, 0 (000f423f) => (000f423f 00000000)
-        mcrf 0, 7 (000f423f) => (f00f423f 00000000)
-        mcrf 7, 0 (000f423f) => (000f4230 00000000)
-        mcrf 7, 7 (000f423f) => (000f423f 00000000)
-        mcrf 0, 0 (ffffffff) => (ffffffff 00000000)
-        mcrf 0, 7 (ffffffff) => (ffffffff 00000000)
-        mcrf 7, 0 (ffffffff) => (ffffffff 00000000)
-        mcrf 7, 7 (ffffffff) => (ffffffff 00000000)
-
-       mcrxr 0 (00000000) => (00000000 00000000)
-       mcrxr 1 (00000000) => (00000000 00000000)
-       mcrxr 2 (00000000) => (00000000 00000000)
-       mcrxr 3 (00000000) => (00000000 00000000)
-       mcrxr 4 (00000000) => (00000000 00000000)
-       mcrxr 5 (00000000) => (00000000 00000000)
-       mcrxr 6 (00000000) => (00000000 00000000)
-       mcrxr 7 (00000000) => (00000000 00000000)
-       mcrxr 0 (10000000) => (00000000 00000000)
-       mcrxr 1 (10000000) => (00000000 00000000)
-       mcrxr 2 (10000000) => (00000000 00000000)
-       mcrxr 3 (10000000) => (00000000 00000000)
-       mcrxr 4 (10000000) => (00000000 00000000)
-       mcrxr 5 (10000000) => (00000000 00000000)
-       mcrxr 6 (10000000) => (00000000 00000000)
-       mcrxr 7 (10000000) => (00000000 00000000)
-       mcrxr 0 (20000000) => (20000000 00000000)
-       mcrxr 1 (20000000) => (02000000 00000000)
-       mcrxr 2 (20000000) => (00200000 00000000)
-       mcrxr 3 (20000000) => (00020000 00000000)
-       mcrxr 4 (20000000) => (00002000 00000000)
-       mcrxr 5 (20000000) => (00000200 00000000)
-       mcrxr 6 (20000000) => (00000020 00000000)
-       mcrxr 7 (20000000) => (00000002 00000000)
-       mcrxr 0 (30000000) => (20000000 00000000)
-       mcrxr 1 (30000000) => (02000000 00000000)
-       mcrxr 2 (30000000) => (00200000 00000000)
-       mcrxr 3 (30000000) => (00020000 00000000)
-       mcrxr 4 (30000000) => (00002000 00000000)
-       mcrxr 5 (30000000) => (00000200 00000000)
-       mcrxr 6 (30000000) => (00000020 00000000)
-       mcrxr 7 (30000000) => (00000002 00000000)
-       mcrxr 0 (40000000) => (40000000 00000000)
-       mcrxr 1 (40000000) => (04000000 00000000)
-       mcrxr 2 (40000000) => (00400000 00000000)
-       mcrxr 3 (40000000) => (00040000 00000000)
-       mcrxr 4 (40000000) => (00004000 00000000)
-       mcrxr 5 (40000000) => (00000400 00000000)
-       mcrxr 6 (40000000) => (00000040 00000000)
-       mcrxr 7 (40000000) => (00000004 00000000)
-       mcrxr 0 (50000000) => (40000000 00000000)
-       mcrxr 1 (50000000) => (04000000 00000000)
-       mcrxr 2 (50000000) => (00400000 00000000)
-       mcrxr 3 (50000000) => (00040000 00000000)
-       mcrxr 4 (50000000) => (00004000 00000000)
-       mcrxr 5 (50000000) => (00000400 00000000)
-       mcrxr 6 (50000000) => (00000040 00000000)
-       mcrxr 7 (50000000) => (00000004 00000000)
-       mcrxr 0 (60000000) => (60000000 00000000)
-       mcrxr 1 (60000000) => (06000000 00000000)
-       mcrxr 2 (60000000) => (00600000 00000000)
-       mcrxr 3 (60000000) => (00060000 00000000)
-       mcrxr 4 (60000000) => (00006000 00000000)
-       mcrxr 5 (60000000) => (00000600 00000000)
-       mcrxr 6 (60000000) => (00000060 00000000)
-       mcrxr 7 (60000000) => (00000006 00000000)
-       mcrxr 0 (70000000) => (60000000 00000000)
-       mcrxr 1 (70000000) => (06000000 00000000)
-       mcrxr 2 (70000000) => (00600000 00000000)
-       mcrxr 3 (70000000) => (00060000 00000000)
-       mcrxr 4 (70000000) => (00006000 00000000)
-       mcrxr 5 (70000000) => (00000600 00000000)
-       mcrxr 6 (70000000) => (00000060 00000000)
-       mcrxr 7 (70000000) => (00000006 00000000)
-       mcrxr 0 (80000000) => (80000000 00000000)
-       mcrxr 1 (80000000) => (08000000 00000000)
-       mcrxr 2 (80000000) => (00800000 00000000)
-       mcrxr 3 (80000000) => (00080000 00000000)
-       mcrxr 4 (80000000) => (00008000 00000000)
-       mcrxr 5 (80000000) => (00000800 00000000)
-       mcrxr 6 (80000000) => (00000080 00000000)
-       mcrxr 7 (80000000) => (00000008 00000000)
-       mcrxr 0 (90000000) => (80000000 00000000)
-       mcrxr 1 (90000000) => (08000000 00000000)
-       mcrxr 2 (90000000) => (00800000 00000000)
-       mcrxr 3 (90000000) => (00080000 00000000)
-       mcrxr 4 (90000000) => (00008000 00000000)
-       mcrxr 5 (90000000) => (00000800 00000000)
-       mcrxr 6 (90000000) => (00000080 00000000)
-       mcrxr 7 (90000000) => (00000008 00000000)
-       mcrxr 0 (a0000000) => (a0000000 00000000)
-       mcrxr 1 (a0000000) => (0a000000 00000000)
-       mcrxr 2 (a0000000) => (00a00000 00000000)
-       mcrxr 3 (a0000000) => (000a0000 00000000)
-       mcrxr 4 (a0000000) => (0000a000 00000000)
-       mcrxr 5 (a0000000) => (00000a00 00000000)
-       mcrxr 6 (a0000000) => (000000a0 00000000)
-       mcrxr 7 (a0000000) => (0000000a 00000000)
-       mcrxr 0 (b0000000) => (a0000000 00000000)
-       mcrxr 1 (b0000000) => (0a000000 00000000)
-       mcrxr 2 (b0000000) => (00a00000 00000000)
-       mcrxr 3 (b0000000) => (000a0000 00000000)
-       mcrxr 4 (b0000000) => (0000a000 00000000)
-       mcrxr 5 (b0000000) => (00000a00 00000000)
-       mcrxr 6 (b0000000) => (000000a0 00000000)
-       mcrxr 7 (b0000000) => (0000000a 00000000)
-       mcrxr 0 (c0000000) => (c0000000 00000000)
-       mcrxr 1 (c0000000) => (0c000000 00000000)
-       mcrxr 2 (c0000000) => (00c00000 00000000)
-       mcrxr 3 (c0000000) => (000c0000 00000000)
-       mcrxr 4 (c0000000) => (0000c000 00000000)
-       mcrxr 5 (c0000000) => (00000c00 00000000)
-       mcrxr 6 (c0000000) => (000000c0 00000000)
-       mcrxr 7 (c0000000) => (0000000c 00000000)
-       mcrxr 0 (d0000000) => (c0000000 00000000)
-       mcrxr 1 (d0000000) => (0c000000 00000000)
-       mcrxr 2 (d0000000) => (00c00000 00000000)
-       mcrxr 3 (d0000000) => (000c0000 00000000)
-       mcrxr 4 (d0000000) => (0000c000 00000000)
-       mcrxr 5 (d0000000) => (00000c00 00000000)
-       mcrxr 6 (d0000000) => (000000c0 00000000)
-       mcrxr 7 (d0000000) => (0000000c 00000000)
-       mcrxr 0 (e0000000) => (e0000000 00000000)
-       mcrxr 1 (e0000000) => (0e000000 00000000)
-       mcrxr 2 (e0000000) => (00e00000 00000000)
-       mcrxr 3 (e0000000) => (000e0000 00000000)
-       mcrxr 4 (e0000000) => (0000e000 00000000)
-       mcrxr 5 (e0000000) => (00000e00 00000000)
-       mcrxr 6 (e0000000) => (000000e0 00000000)
-       mcrxr 7 (e0000000) => (0000000e 00000000)
-       mcrxr 0 (f0000000) => (e0000000 00000000)
-       mcrxr 1 (f0000000) => (0e000000 00000000)
-       mcrxr 2 (f0000000) => (00e00000 00000000)
-       mcrxr 3 (f0000000) => (000e0000 00000000)
-       mcrxr 4 (f0000000) => (0000e000 00000000)
-       mcrxr 5 (f0000000) => (00000e00 00000000)
-       mcrxr 6 (f0000000) => (000000e0 00000000)
-       mcrxr 7 (f0000000) => (0000000e 00000000)
-
-       mtcrf   0, 00000000 => (00000000 00000000)
-       mtcrf  99, 00000000 => (00000000 00000000)
-       mtcrf 198, 00000000 => (00000000 00000000)
-       mtcrf   0, 000f423f => (00000000 00000000)
-       mtcrf  99, 000f423f => (0000003f 00000000)
-       mtcrf 198, 000f423f => (00000230 00000000)
-       mtcrf   0, ffffffff => (00000000 00000000)
-       mtcrf  99, ffffffff => (0ff000ff 00000000)
-       mtcrf 198, ffffffff => (ff000ff0 00000000)
-
-PPC integer load insns
-    with one register + one 16 bits immediate args with flags update:
-         lbz  0, (00000000) => 00000000,  0 (00000000 00000000)
-         lbz  3, (000f423f) => 00000000,  0 (00000000 00000000)
-         lbz  7, (ffffffff) => 0000003f,  0 (00000000 00000000)
-         lbz  1, (ffffffff) => 000000ff,  0 (00000000 00000000)
-         lbz -3, (000f423f) => 0000000f,  0 (00000000 00000000)
-         lbz -7, (00000000) => 00000000,  0 (00000000 00000000)
-
-        lbzu  0, (00000000) => 00000000,  0 (00000000 00000000)
-        lbzu  3, (000f423f) => 00000000,  3 (00000000 00000000)
-        lbzu  7, (ffffffff) => 0000003f,  7 (00000000 00000000)
-        lbzu  1, (ffffffff) => 000000ff,  1 (00000000 00000000)
-        lbzu -3, (000f423f) => 0000000f, -3 (00000000 00000000)
-        lbzu -7, (00000000) => 00000000, -7 (00000000 00000000)
-
-         lha  0, (00000000) => 00000000,  0 (00000000 00000000)
-         lha  3, (000f423f) => 00000000,  0 (00000000 00000000)
-         lha  7, (ffffffff) => 00003fff,  0 (00000000 00000000)
-         lha  1, (ffffffff) => ffffffff,  0 (00000000 00000000)
-         lha -3, (000f423f) => 00000f42,  0 (00000000 00000000)
-         lha -7, (00000000) => 00000000,  0 (00000000 00000000)
-
-        lhau  0, (00000000) => 00000000,  0 (00000000 00000000)
-        lhau  3, (000f423f) => 00000000,  3 (00000000 00000000)
-        lhau  7, (ffffffff) => 00003fff,  7 (00000000 00000000)
-        lhau  1, (ffffffff) => ffffffff,  1 (00000000 00000000)
-        lhau -3, (000f423f) => 00000f42, -3 (00000000 00000000)
-        lhau -7, (00000000) => 00000000, -7 (00000000 00000000)
-
-         lhz  0, (00000000) => 00000000,  0 (00000000 00000000)
-         lhz  3, (000f423f) => 00000000,  0 (00000000 00000000)
-         lhz  7, (ffffffff) => 00003fff,  0 (00000000 00000000)
-         lhz  1, (ffffffff) => 0000ffff,  0 (00000000 00000000)
-         lhz -3, (000f423f) => 00000f42,  0 (00000000 00000000)
-         lhz -7, (00000000) => 00000000,  0 (00000000 00000000)
-
-        lhzu  0, (00000000) => 00000000,  0 (00000000 00000000)
-        lhzu  3, (000f423f) => 00000000,  3 (00000000 00000000)
-        lhzu  7, (ffffffff) => 00003fff,  7 (00000000 00000000)
-        lhzu  1, (ffffffff) => 0000ffff,  1 (00000000 00000000)
-        lhzu -3, (000f423f) => 00000f42, -3 (00000000 00000000)
-        lhzu -7, (00000000) => 00000000, -7 (00000000 00000000)
-
-         lwz  0, (00000000) => 00000000,  0 (00000000 00000000)
-         lwz  3, (000f423f) => 00000f42,  0 (00000000 00000000)
-         lwz  7, (ffffffff) => 3fffffff,  0 (00000000 00000000)
-         lwz  1, (ffffffff) => ffffff00,  0 (00000000 00000000)
-         lwz -3, (000f423f) => 0f423fff,  0 (00000000 00000000)
-         lwz -7, (00000000) => 00000000,  0 (00000000 00000000)
-
-        lwzu  0, (00000000) => 00000000,  0 (00000000 00000000)
-        lwzu  3, (000f423f) => 00000f42,  3 (00000000 00000000)
-        lwzu  7, (ffffffff) => 3fffffff,  7 (00000000 00000000)
-        lwzu  1, (ffffffff) => ffffff00,  1 (00000000 00000000)
-        lwzu -3, (000f423f) => 0f423fff, -3 (00000000 00000000)
-        lwzu -7, (00000000) => 00000000, -7 (00000000 00000000)
-
-PPC integer load insns with two register args:
-        lbzx 0 (00000000) => 00000000, 0 (00000000 00000000)
-        lbzx 4 (000f423f) => 00000000, 0 (00000000 00000000)
-        lbzx 8 (ffffffff) => 000000ff, 0 (00000000 00000000)
-
-       lbzux 0 (00000000) => 00000000, 0 (00000000 00000000)
-       lbzux 4 (000f423f) => 00000000, 4 (00000000 00000000)
-       lbzux 8 (ffffffff) => 000000ff, 8 (00000000 00000000)
-
-        lhax 0 (00000000) => 00000000, 0 (00000000 00000000)
-        lhax 4 (000f423f) => 0000000f, 0 (00000000 00000000)
-        lhax 8 (ffffffff) => ffffffff, 0 (00000000 00000000)
-
-       lhaux 0 (00000000) => 00000000, 0 (00000000 00000000)
-       lhaux 4 (000f423f) => 0000000f, 4 (00000000 00000000)
-       lhaux 8 (ffffffff) => ffffffff, 8 (00000000 00000000)
-
-        lhzx 0 (00000000) => 00000000, 0 (00000000 00000000)
-        lhzx 4 (000f423f) => 0000000f, 0 (00000000 00000000)
-        lhzx 8 (ffffffff) => 0000ffff, 0 (00000000 00000000)
-
-       lhzux 0 (00000000) => 00000000, 0 (00000000 00000000)
-       lhzux 4 (000f423f) => 0000000f, 4 (00000000 00000000)
-       lhzux 8 (ffffffff) => 0000ffff, 8 (00000000 00000000)
-
-        lwzx 0 (00000000) => 00000000, 0 (00000000 00000000)
-        lwzx 4 (000f423f) => 000f423f, 0 (00000000 00000000)
-        lwzx 8 (ffffffff) => ffffffff, 0 (00000000 00000000)
-
-       lwzux 0 (00000000) => 00000000, 0 (00000000 00000000)
-       lwzux 4 (000f423f) => 000f423f, 4 (00000000 00000000)
-       lwzux 8 (ffffffff) => ffffffff, 8 (00000000 00000000)
-
-PPC integer store insns
-    with one register + one 16 bits immediate args with flags update:
-         stb 00000000,  0 => 00000000,  0 (00000000 00000000)
-         stb 000f423f,  4 => 3f000000,  0 (00000000 00000000)
-         stb ffffffff,  8 => ff000000,  0 (00000000 00000000)
-         stb 00000000, -8 => 00000000,  0 (00000000 00000000)
-         stb 000f423f, -4 => 3f000000,  0 (00000000 00000000)
-         stb ffffffff,  0 => ff000000,  0 (00000000 00000000)
-
-        stbu 00000000,  0 => 00000000,  0 (00000000 00000000)
-        stbu 000f423f,  4 => 3f000000,  4 (00000000 00000000)
-        stbu ffffffff,  8 => ff000000,  8 (00000000 00000000)
-        stbu 00000000, -8 => 00000000, -8 (00000000 00000000)
-        stbu 000f423f, -4 => 3f000000, -4 (00000000 00000000)
-        stbu ffffffff,  0 => ff000000,  0 (00000000 00000000)
-
-         sth 00000000,  0 => 00000000,  0 (00000000 00000000)
-         sth 000f423f,  4 => 423f0000,  0 (00000000 00000000)
-         sth ffffffff,  8 => ffff0000,  0 (00000000 00000000)
-         sth 00000000, -8 => 00000000,  0 (00000000 00000000)
-         sth 000f423f, -4 => 423f0000,  0 (00000000 00000000)
-         sth ffffffff,  0 => ffff0000,  0 (00000000 00000000)
-
-        sthu 00000000,  0 => 00000000,  0 (00000000 00000000)
-        sthu 000f423f,  4 => 423f0000,  4 (00000000 00000000)
-        sthu ffffffff,  8 => ffff0000,  8 (00000000 00000000)
-        sthu 00000000, -8 => 00000000, -8 (00000000 00000000)
-        sthu 000f423f, -4 => 423f0000, -4 (00000000 00000000)
-        sthu ffffffff,  0 => ffff0000,  0 (00000000 00000000)
-
-         stw 00000000,  0 => 00000000,  0 (00000000 00000000)
-         stw 000f423f,  4 => 000f423f,  0 (00000000 00000000)
-         stw ffffffff,  8 => ffffffff,  0 (00000000 00000000)
-         stw 00000000, -8 => 00000000,  0 (00000000 00000000)
-         stw 000f423f, -4 => 000f423f,  0 (00000000 00000000)
-         stw ffffffff,  0 => ffffffff,  0 (00000000 00000000)
-
-        stwu 00000000,  0 => 00000000,  0 (00000000 00000000)
-        stwu 000f423f,  4 => 000f423f,  4 (00000000 00000000)
-        stwu ffffffff,  8 => ffffffff,  8 (00000000 00000000)
-        stwu 00000000, -8 => 00000000, -8 (00000000 00000000)
-        stwu 000f423f, -4 => 000f423f, -4 (00000000 00000000)
-        stwu ffffffff,  0 => ffffffff,  0 (00000000 00000000)
-
-PPC integer store insns with three register args:
-        stbx 00000000, 0 => 00000000, 0 (00000000 00000000)
-        stbx 000f423f, 4 => 3f000000, 0 (00000000 00000000)
-        stbx ffffffff, 8 => ff000000, 0 (00000000 00000000)
-
-       stbux 00000000, 0 => 00000000, 0 (00000000 00000000)
-       stbux 000f423f, 4 => 3f000000, 4 (00000000 00000000)
-       stbux ffffffff, 8 => ff000000, 8 (00000000 00000000)
-
-        sthx 00000000, 0 => 00000000, 0 (00000000 00000000)
-        sthx 000f423f, 4 => 423f0000, 0 (00000000 00000000)
-        sthx ffffffff, 8 => ffff0000, 0 (00000000 00000000)
-
-       sthux 00000000, 0 => 00000000, 0 (00000000 00000000)
-       sthux 000f423f, 4 => 423f0000, 4 (00000000 00000000)
-       sthux ffffffff, 8 => ffff0000, 8 (00000000 00000000)
-
-        stwx 00000000, 0 => 00000000, 0 (00000000 00000000)
-        stwx 000f423f, 4 => 000f423f, 0 (00000000 00000000)
-        stwx ffffffff, 8 => ffffffff, 0 (00000000 00000000)
-
-       stwux 00000000, 0 => 00000000, 0 (00000000 00000000)
-       stwux 000f423f, 4 => 000f423f, 4 (00000000 00000000)
-       stwux ffffffff, 8 => ffffffff, 8 (00000000 00000000)
-
 PPC integer population count with one register args, no flags:
         popcntb 00000000 => 00000000 (00000000 00000000)
         popcntb 000f423f => 00040206 (00000000 00000000)
         popcntb ffffffff => 08080808 (00000000 00000000)
 
-All done. Tested 155 different instructions
+All done. Tested 63 different instructions

Modified: trunk/none/tests/ppc32/test_isa_2_06_part2.c
==============================================================================
--- trunk/none/tests/ppc32/test_isa_2_06_part2.c (original)
+++ trunk/none/tests/ppc32/test_isa_2_06_part2.c Wed May  3 18:28:35 2017
@@ -29,6 +29,7 @@
 #include <malloc.h>
 #include <altivec.h>
 #include <math.h>
+#include <unistd.h>    // getopt
 
 #ifndef __powerpc64__
 typedef uint32_t HWord_t;
@@ -92,6 +93,9 @@
 typedef void (*test_func_t)(void);
 typedef struct test_table test_table_t;
 
+/* Defines for the instructiion groups, use bit field to identify */
+#define SCALAR_DIV_INST    0x0001
+#define OTHER_INST  0x0002
 
 /* These functions below that construct a table of floating point
  * values were lifted from none/tests/ppc32/jm-insns.c.
@@ -541,6 +545,7 @@
 {
    test_func_t test_category;
    char * name;
+   unsigned int test_group;
 };
 
 typedef enum {
@@ -1741,33 +1746,44 @@
          all_tests[] =
 {
                     { &test_vx_vector_one_fp_arg,
-                      "Test VSX vector single arg instructions"},
+                      "Test VSX vector single arg instructions", OTHER_INST },
                     { &test_vx_vector_fp_ops,
-                      "Test VSX floating point compare and basic arithmetic instructions" },
+                      "Test VSX floating point compare and basic arithmetic instructions", OTHER_INST },
 #ifdef __powerpc64__
                      { &test_bpermd,
-                       "Test bit permute double"},
+                       "Test bit permute double", OTHER_INST },
 #endif
                      { &test_xxsel,
-                         "Test xxsel instruction" },
+                         "Test xxsel instruction", OTHER_INST },
                      { &test_xxspltw,
-                         "Test xxspltw instruction" },
+                         "Test xxspltw instruction", OTHER_INST },
                      { &test_div_extensions,
-                       "Test div extensions" },
+                       "Test div extensions", SCALAR_DIV_INST },
                      { &test_fct_ops,
-                       "Test floating point convert [word | doubleword] unsigned, with round toward zero" },
+                       "Test floating point convert [word | doubleword] unsigned, with round toward zero", OTHER_INST },
 #ifdef __powerpc64__
                      { &test_stdbrx,
-                      "Test stdbrx instruction"},
+                      "Test stdbrx instruction", OTHER_INST },
 #endif
                      { &test_vx_aORm_fp_ops,
-                      "Test floating point arithmetic instructions -- with a{d|s}p or m{d|s}p"},
+       "Test floating point arithmetic instructions -- with a{d|s}p or m{d|s}p", OTHER_INST },
                      { &test_vx_simple_scalar_fp_ops,
-                      "Test scalar floating point arithmetic instructions"},
+                      "Test scalar floating point arithmetic instructions", OTHER_INST },
                      { NULL, NULL }
 };
 #endif // HAS_VSX
 
+static void usage (void)
+{
+  fprintf(stderr,
+  "Usage: test_isa_3_0 [OPTIONS]\n"
+  "\t-d: test scalar division instructions (default)\n"
+  "\t-o: test non scalar division instructions (default)\n"
+  "\t-A: test all instructions (default)\n"
+  "\t-h: display this help and exit\n"
+  );
+}
+
 int main(int argc, char *argv[])
 {
 #ifdef HAS_VSX
@@ -1775,11 +1791,47 @@
    test_table_t aTest;
    test_func_t func;
    int i = 0;
+   int c;
+   unsigned int test_run_mask = 0;
+
+   /* NOTE, ISA 3.0 introduces the OV32 and CA32 bits in the FPSCR. These
+    * bits are set on various arithimetic instructions.  This means this
+    * test generates different FPSCR output for pre ISA 3.0 versus ISA 3.0
+    * hardware.  The tests have been grouped so that the tests that generate
+    * different results are in one test and the rest are in a different test.
+    * this minimizes the size of the result expect files for the two cases.
+    */
+
+   while ((c = getopt(argc, argv, "doAh")) != -1) {
+      switch (c) {
+      case 'd':
+ test_run_mask |= SCALAR_DIV_INST;
+         break;
+      case 'o':
+ test_run_mask |= OTHER_INST;
+         break;
+      case 'A':
+ test_run_mask = 0xFFFF;
+         break;
+      case 'h':
+         usage();
+         return 0;
+
+      default:
+         usage();
+         fprintf(stderr, "Unknown argument: '%c'\n", c);
+         return 1;
+      }
+   }
 
    while ((func = all_tests[i].test_category)) {
       aTest = all_tests[i];
-      printf( "%s\n", aTest.name );
-      (*func)();
+      if(test_run_mask & aTest.test_group) {
+ /* Test group  specified on command line */
+
+ printf( "%s\n", aTest.name );
+ (*func)();
+      }
       i++;
    }
    if (spec_fargs)

Modified: trunk/none/tests/ppc32/test_isa_2_06_part2.stdout.exp
==============================================================================
--- trunk/none/tests/ppc32/test_isa_2_06_part2.stdout.exp (original)
+++ trunk/none/tests/ppc32/test_isa_2_06_part2.stdout.exp Wed May  3 18:28:35 2017
@@ -699,37 +699,6 @@
 xxspltw 0xfedc432124681235f1e2d3c4e0057708 2=> 0xf1e2d3c4f1e2d3c4f1e2d3c4f1e2d3c4
 xxspltw 0xfedc432124681235f1e2d3c4e0057708 3=> 0xe0057708e0057708e0057708e0057708
 
-Test div extensions
-#0: divweu: 0x00000000 / 0x00000002 = 0x00000000; CR=0; XER=0
-#1: divweu: 0x00000002 / 0x00000000 = 0x00000000; CR=0; XER=0
-#2: divweu: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=0; XER=0
-#3: divweu: 0xfabc1234 / 0x00000005 = 0x00000000; CR=0; XER=0
-#4: divweu: 0x0000004d / 0x00000042 = 0x00000000; CR=0; XER=0
-#5: divweu: 0x00000005 / 0xfabc1234 = 0x00000005; CR=0; XER=0
-
-#0: divweu.: 0x00000000 / 0x00000002 = 0x00000000; CR=2; XER=0
-#1: divweu.: 0x00000002 / 0x00000000 = 0x00000000; CR=2; XER=0
-#2: divweu.: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=8; XER=0
-#3: divweu.: 0xfabc1234 / 0x00000005 = 0x00000000; CR=2; XER=0
-#4: divweu.: 0x0000004d / 0x00000042 = 0x00000000; CR=2; XER=0
-#5: divweu.: 0x00000005 / 0xfabc1234 = 0x00000005; CR=4; XER=0
-
-
-#0: divweuo: 0x00000000 / 0x00000002 = 0x00000000; CR=0; XER=0
-#1: divweuo: 0x00000002 / 0x00000000 = 0x00000000; CR=0; XER=c0000000
-#2: divweuo: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=0; XER=0
-#3: divweuo: 0xfabc1234 / 0x00000005 = 0x00000000; CR=0; XER=c0000000
-#4: divweuo: 0x0000004d / 0x00000042 = 0x00000000; CR=0; XER=c0000000
-#5: divweuo: 0x00000005 / 0xfabc1234 = 0x00000005; CR=0; XER=0
-
-#0: divweuo.: 0x00000000 / 0x00000002 = 0x00000000; CR=2; XER=0
-#1: divweuo.: 0x00000002 / 0x00000000 = 0x00000000; CR=3; XER=c0000000
-#2: divweuo.: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=8; XER=0
-#3: divweuo.: 0xfabc1234 / 0x00000005 = 0x00000000; CR=3; XER=c0000000
-#4: divweuo.: 0x0000004d / 0x00000042 = 0x00000000; CR=3; XER=c0000000
-#5: divweuo.: 0x00000005 / 0xfabc1234 = 0x00000005; CR=4; XER=0
-
-
 Test floating point convert [word | doubleword] unsigned, with round toward zero
 #0: fctiduz: 0x3fd8000000000000 (3.750000e-01) ==> 0x0000000000000000
 #1: fctiduz: 0x404f000000000000 (6.200000e+01) ==> 0x000000000000003e

Modified: trunk/none/tests/ppc32/test_isa_2_06_part2.vgtest
==============================================================================
--- trunk/none/tests/ppc32/test_isa_2_06_part2.vgtest (original)
+++ trunk/none/tests/ppc32/test_isa_2_06_part2.vgtest Wed May  3 18:28:35 2017
@@ -1,2 +1,2 @@
 prereq: ../../../tests/check_ppc64_auxv_cap arch_2_06
-prog: test_isa_2_06_part2
+prog: test_isa_2_06_part2  -o

Modified: trunk/none/tests/ppc32/test_isa_2_06_part3.c
==============================================================================
--- trunk/none/tests/ppc32/test_isa_2_06_part3.c (original)
+++ trunk/none/tests/ppc32/test_isa_2_06_part3.c Wed May  3 18:28:35 2017
@@ -29,6 +29,7 @@
 #include <malloc.h>
 #include <altivec.h>
 #include <math.h>
+#include <unistd.h>    // getopt
 
 #ifndef __powerpc64__
 typedef uint32_t HWord_t;
@@ -91,6 +92,9 @@
 typedef void (*test_func_t)(void);
 typedef struct test_table test_table_t;
 
+/* Defines for the instructiion groups, use bit field to identify */
+#define SCALAR_DIV_INST    0x0001
+#define OTHER_INST  0x0002
 
 /* These functions below that construct a table of floating point
  * values were lifted from none/tests/ppc32/jm-insns.c.
@@ -401,6 +405,7 @@
 {
    test_func_t test_category;
    char * name;
+   unsigned int test_group;
 };
 
 /*  Type of input for floating point operations.*/
@@ -1586,33 +1591,81 @@
 {
 
                     { &test_vsx_one_fp_arg,
-                      "Test VSX vector and scalar single argument instructions"} ,
+                      "Test VSX vector and scalar single argument instructions", OTHER_INST } ,
                     { &test_int_to_fp_convert,
-                      "Test VSX vector integer to float conversion instructions" },
+                      "Test VSX vector integer to float conversion instructions", OTHER_INST },
                     { &test_div_extensions,
-                       "Test div extensions" },
+      "Test div extensions", SCALAR_DIV_INST },
                     { &test_ftsqrt,
-                       "Test ftsqrt instruction" },
+      "Test ftsqrt instruction", OTHER_INST },
                     { &test_vx_tdivORtsqrt,
-                       "Test vector and scalar tdiv and tsqrt instructions" },
+      "Test vector and scalar tdiv and tsqrt instructions", OTHER_INST },
                     { &test_popcntw,
-                       "Test popcntw instruction" },
+      "Test popcntw instruction", OTHER_INST },
                     { NULL, NULL }
 };
 #endif // HAS_VSX
 
-int main(int argc, char *argv[])
+static void usage (void)
+{
+  fprintf(stderr,
+  "Usage: test_isa_3_0 [OPTIONS]\n"
+  "\t-d: test scalar division instructions (default)\n"
+  "\t-o: test non scalar division instructions (default)\n"
+  "\t-A: test all instructions (default)\n"
+  "\t-h: display this help and exit\n"
+  );
+}
+
+int main(int argc, char **argv)
 {
 #ifdef HAS_VSX
 
    test_table_t aTest;
    test_func_t func;
+   int c;
    int i = 0;
+   unsigned int test_run_mask = 0;
+
+   /* NOTE, ISA 3.0 introduces the OV32 and CA32 bits in the FPSCR. These
+    * bits are set on various arithimetic instructions.  This means this
+    * test generates different FPSCR output for pre ISA 3.0 versus ISA 3.0
+    * hardware.  The tests have been grouped so that the tests that generate
+    * different results are in one test and the rest are in a different test.
+    * this minimizes the size of the result expect files for the two cases.
+    */
+
+   while ((c = getopt(argc, argv, "doAh")) != -1) {
+      switch (c) {
+      case 'd':
+ test_run_mask |= SCALAR_DIV_INST;
+         break;
+      case 'o':
+ test_run_mask |= OTHER_INST;
+         break;
+      case 'A':
+ test_run_mask = 0xFFFF;
+         break;
+      case 'h':
+         usage();
+         return 0;
+
+      default:
+         usage();
+         fprintf(stderr, "Unknown argument: '%c'\n", c);
+         return 1;
+      }
+   }
 
    while ((func = all_tests[i].test_category)) {
       aTest = all_tests[i];
-      printf( "%s\n", aTest.name );
-      (*func)();
+
+      if(test_run_mask & aTest.test_group) {
+ /* Test group  specified on command line */
+
+ printf( "%s\n", aTest.name );
+ (*func)();
+      }
       i++;
    }
    if (spec_fargs)

Modified: trunk/none/tests/ppc32/test_isa_2_06_part3.stdout.exp
==============================================================================
--- trunk/none/tests/ppc32/test_isa_2_06_part3.stdout.exp (original)
+++ trunk/none/tests/ppc32/test_isa_2_06_part3.stdout.exp Wed May  3 18:28:35 2017
@@ -455,37 +455,6 @@
 #0: xvcvuxwsp conv(00000000) = 00000000; conv(ffff0000) = 4f7fff00; conv(0000ffff) = 477fff00; conv(ffffffff) = 4f800000
 #1: xvcvuxwsp conv(89a73522) = 4f09a735; conv(01020304) = 4b810182; conv(0000abcd) = 472bcd00; conv(11223344) = 4d89119a
 
-Test div extensions
-#0: divwe: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=0; XER=0
-#1: divwe: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=0; XER=0
-#2: divwe: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=0; XER=0
-#3: divwe: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=0; XER=0
-#4: divwe: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=0; XER=0
-#5: divwe: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=0; XER=0
-
-#0: divwe.: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=2; XER=0
-#1: divwe.: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=2; XER=0
-#2: divwe.: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=2; XER=0
-#3: divwe.: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=2; XER=0
-#4: divwe.: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=2; XER=0
-#5: divwe.: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=8; XER=0
-
-
-#0: divweo: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=0; XER=0
-#1: divweo: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=0; XER=c0000000
-#2: divweo: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=0; XER=c0000000
-#3: divweo: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=0; XER=c0000000
-#4: divweo: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=0; XER=c0000000
-#5: divweo: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=0; XER=0
-
-#0: divweo.: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=2; XER=0
-#1: divweo.: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=3; XER=c0000000
-#2: divweo.: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=3; XER=c0000000
-#3: divweo.: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=3; XER=c0000000
-#4: divweo.: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=3; XER=c0000000
-#5: divweo.: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=8; XER=0
-
-
 Test ftsqrt instruction
 ftsqrt: 3fd8000000000000 ? 8 (CRx)
 ftsqrt: 404f000000000000 ? 8 (CRx)

Modified: trunk/none/tests/ppc32/test_isa_2_06_part3.vgtest
==============================================================================
--- trunk/none/tests/ppc32/test_isa_2_06_part3.vgtest (original)
+++ trunk/none/tests/ppc32/test_isa_2_06_part3.vgtest Wed May  3 18:28:35 2017
@@ -1,2 +1,2 @@
 prereq: ../../../tests/check_ppc64_auxv_cap arch_2_06
-prog: test_isa_2_06_part3
+prog: test_isa_2_06_part3  -o

Modified: trunk/none/tests/ppc64/Makefile.am
==============================================================================
--- trunk/none/tests/ppc64/Makefile.am (original)
+++ trunk/none/tests/ppc64/Makefile.am Wed May  3 18:28:35 2017
@@ -7,6 +7,9 @@
 
 EXTRA_DIST = \
  jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest jm-int.stdout.exp-LE \
+   jm-int.stdout.exp-LE-ISA3_0 \
+ jm-int_other.stderr.exp jm-int_other.stdout.exp jm-int_other.vgtest \
+ jm-int_other.stdout.exp-LE \
  jm-fp.stderr.exp  jm-fp.stdout.exp  jm-fp.vgtest jm-fp.stdout.exp-LE jm-fp.stdout.exp-LE2 jm-fp.stdout.exp-BE2 \
  jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.stdout.exp_Minus_nan jm-vmx.stdout.exp-LE \
  jm-vmx.vgtest \
@@ -22,7 +25,11 @@
  test_isa_2_06_part1.stderr.exp  test_isa_2_06_part1.stdout.exp  test_isa_2_06_part1.vgtest \
  test_isa_2_06_part1.stdout.exp-LE \
  test_isa_2_06_part2.stderr.exp  test_isa_2_06_part2.stdout.exp  test_isa_2_06_part2.vgtest \
+ test_isa_2_06_part2-div.stderr.exp  test_isa_2_06_part2-div.stdout.exp \
+ test_isa_2_06_part2-div.stdout.exp-LE-ISA3_0 test_isa_2_06_part2-div.vgtest \
  test_isa_2_06_part3.stderr.exp  test_isa_2_06_part3.stdout.exp  test_isa_2_06_part3.vgtest \
+ test_isa_2_06_part3-div.stderr.exp  test_isa_2_06_part3-div.stdout.exp \
+ test_isa_2_06_part3-div.stdout.exp-LE-ISA3_0  test_isa_2_06_part3-div.vgtest \
  test_dfp1.stderr.exp test_dfp1.stdout.exp test_dfp1.vgtest \
  test_dfp2.stderr.exp test_dfp2.stdout.exp test_dfp2.vgtest \
  test_dfp2.stdout.exp_Without_dcffix \

Modified: trunk/none/tests/ppc64/jm-int.stdout.exp
==============================================================================
--- trunk/none/tests/ppc64/jm-int.stdout.exp (original)
+++ trunk/none/tests/ppc64/jm-int.stdout.exp Wed May  3 18:28:35 2017
@@ -610,370 +610,6 @@
      subfeo. ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
      subfeo. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 20000000)
 
-PPC integer logical insns with two args:
-         and 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
-         and 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
-         and 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-         and 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
-         and 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
-         and 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 00000000)
-         and ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
-         and ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
-         and ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
-
-        andc 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
-        andc 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
-        andc 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-        andc 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
-        andc 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
-        andc 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-        andc ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
-        andc ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
-        andc ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-
-         eqv 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
-         eqv 0000000000000000, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
-         eqv 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-         eqv 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (00000000 00000000)
-         eqv 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
-         eqv 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 00000000)
-         eqv ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
-         eqv ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
-         eqv ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
-
-        nand 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
-        nand 0000000000000000, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
-        nand 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
-        nand 0000001cbe991def, 0000000000000000 => ffffffffffffffff (00000000 00000000)
-        nand 0000001cbe991def, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
-        nand 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 00000000)
-        nand ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
-        nand ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
-        nand ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-
-         nor 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
-         nor 0000000000000000, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
-         nor 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-         nor 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (00000000 00000000)
-         nor 0000001cbe991def, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
-         nor 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-         nor ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
-         nor ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
-         nor ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-
-          or 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
-          or 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
-          or 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
-          or 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
-          or 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
-          or 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
-          or ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
-          or ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
-          or ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
-
-         orc 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
-         orc 0000000000000000, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
-         orc 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-         orc 0000001cbe991def, 0000000000000000 => ffffffffffffffff (00000000 00000000)
-         orc 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
-         orc 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 00000000)
-         orc ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
-         orc ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
-         orc ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
-
-         xor 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
-         xor 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
-         xor 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
-         xor 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
-         xor 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
-         xor 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 00000000)
-         xor ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
-         xor ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
-         xor ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-
-         slw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
-         slw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
-         slw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-         slw 0000001cbe991def, 0000000000000000 => 00000000be991def (00000000 00000000)
-         slw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
-         slw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-         slw ffffffffffffffff, 0000000000000000 => 00000000ffffffff (00000000 00000000)
-         slw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
-         slw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-
-        sraw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
-        sraw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
-        sraw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-        sraw 0000001cbe991def, 0000000000000000 => ffffffffbe991def (00000000 00000000)
-        sraw 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 20000000)
-        sraw 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
-        sraw ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
-        sraw ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 20000000)
-        sraw ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
-
-         srw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
-         srw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
-         srw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-         srw 0000001cbe991def, 0000000000000000 => 00000000be991def (00000000 00000000)
-         srw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
-         srw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-         srw ffffffffffffffff, 0000000000000000 => 00000000ffffffff (00000000 00000000)
-         srw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
-         srw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-
-         sld 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
-         sld 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
-         sld 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-         sld 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
-         sld 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
-         sld 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-         sld ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
-         sld ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
-         sld ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-
-        srad 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
-        srad 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
-        srad 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
-        srad 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)

[... 49037 lines stripped ...]

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