Quantcast

Valgrind: r16330 - in /trunk/none/tests: ppc32/ ppc64/

classic Classic list List threaded Threaded
1 message Options
Reply | Threaded
Open this post in threaded view
|  
Report Content as Inappropriate

Valgrind: r16330 - in /trunk/none/tests: ppc32/ ppc64/

svn-2
Author: carll
Date: Wed May  3 19:15:01 2017
New Revision: 16330

Log:
Updated  PPC64 ISA 3.0B, add support for the additional instructions: addex, mffscdrn,
mffscdrni, mffsce, mffscrn, mffscrni, mffsl. vmsumudm.

Forgot to add the new files.  


Vex commit 3359  Has the source code changes for the instruction and OV32, CS32
support

Valgrind commit 16329 updated the existing files

This commit adds all the new files.  

Valgrind bugzilla 378931

Added:
    trunk/none/tests/ppc32/jm-int_other.stderr.exp
    trunk/none/tests/ppc32/jm-int_other.stdout.exp
    trunk/none/tests/ppc32/jm-int_other.vgtest
    trunk/none/tests/ppc32/test_isa_2_06_part2-div.stderr.exp
    trunk/none/tests/ppc32/test_isa_2_06_part2-div.stdout.exp
    trunk/none/tests/ppc32/test_isa_2_06_part2-div.vgtest
    trunk/none/tests/ppc32/test_isa_2_06_part3-div.stderr.exp
    trunk/none/tests/ppc32/test_isa_2_06_part3-div.stdout.exp
    trunk/none/tests/ppc32/test_isa_2_06_part3-div.vgtest
    trunk/none/tests/ppc64/jm-int.stdout.exp-LE-ISA3_0
    trunk/none/tests/ppc64/jm-int_other.stderr.exp
    trunk/none/tests/ppc64/jm-int_other.stdout.exp
    trunk/none/tests/ppc64/jm-int_other.stdout.exp-LE
    trunk/none/tests/ppc64/jm-int_other.vgtest
    trunk/none/tests/ppc64/test_isa_2_06_part2-div.stderr.exp
    trunk/none/tests/ppc64/test_isa_2_06_part2-div.stdout.exp
    trunk/none/tests/ppc64/test_isa_2_06_part2-div.stdout.exp-LE-ISA3_0
    trunk/none/tests/ppc64/test_isa_2_06_part2-div.vgtest
    trunk/none/tests/ppc64/test_isa_2_06_part3-div.stderr.exp
    trunk/none/tests/ppc64/test_isa_2_06_part3-div.stdout.exp
    trunk/none/tests/ppc64/test_isa_2_06_part3-div.stdout.exp-LE-ISA3_0
    trunk/none/tests/ppc64/test_isa_2_06_part3-div.vgtest

Added: trunk/none/tests/ppc32/jm-int_other.stderr.exp
==============================================================================
--- trunk/none/tests/ppc32/jm-int_other.stderr.exp (added)
+++ trunk/none/tests/ppc32/jm-int_other.stderr.exp Wed May  3 19:15:01 2017
@@ -0,0 +1,2 @@
+
+

Added: trunk/none/tests/ppc32/jm-int_other.stdout.exp
==============================================================================
--- trunk/none/tests/ppc32/jm-int_other.stdout.exp (added)
+++ trunk/none/tests/ppc32/jm-int_other.stdout.exp Wed May  3 19:15:01 2017
@@ -0,0 +1,969 @@
+PPC integer logical insns with two args:
+         and 00000000, 00000000 => 00000000 (00000000 00000000)
+         and 00000000, 000f423f => 00000000 (00000000 00000000)
+         and 00000000, ffffffff => 00000000 (00000000 00000000)
+         and 000f423f, 00000000 => 00000000 (00000000 00000000)
+         and 000f423f, 000f423f => 000f423f (00000000 00000000)
+         and 000f423f, ffffffff => 000f423f (00000000 00000000)
+         and ffffffff, 00000000 => 00000000 (00000000 00000000)
+         and ffffffff, 000f423f => 000f423f (00000000 00000000)
+         and ffffffff, ffffffff => ffffffff (00000000 00000000)
+
+        andc 00000000, 00000000 => 00000000 (00000000 00000000)
+        andc 00000000, 000f423f => 00000000 (00000000 00000000)
+        andc 00000000, ffffffff => 00000000 (00000000 00000000)
+        andc 000f423f, 00000000 => 000f423f (00000000 00000000)
+        andc 000f423f, 000f423f => 00000000 (00000000 00000000)
+        andc 000f423f, ffffffff => 00000000 (00000000 00000000)
+        andc ffffffff, 00000000 => ffffffff (00000000 00000000)
+        andc ffffffff, 000f423f => fff0bdc0 (00000000 00000000)
+        andc ffffffff, ffffffff => 00000000 (00000000 00000000)
+
+         eqv 00000000, 00000000 => ffffffff (00000000 00000000)
+         eqv 00000000, 000f423f => fff0bdc0 (00000000 00000000)
+         eqv 00000000, ffffffff => 00000000 (00000000 00000000)
+         eqv 000f423f, 00000000 => fff0bdc0 (00000000 00000000)
+         eqv 000f423f, 000f423f => ffffffff (00000000 00000000)
+         eqv 000f423f, ffffffff => 000f423f (00000000 00000000)
+         eqv ffffffff, 00000000 => 00000000 (00000000 00000000)
+         eqv ffffffff, 000f423f => 000f423f (00000000 00000000)
+         eqv ffffffff, ffffffff => ffffffff (00000000 00000000)
+
+        nand 00000000, 00000000 => ffffffff (00000000 00000000)
+        nand 00000000, 000f423f => ffffffff (00000000 00000000)
+        nand 00000000, ffffffff => ffffffff (00000000 00000000)
+        nand 000f423f, 00000000 => ffffffff (00000000 00000000)
+        nand 000f423f, 000f423f => fff0bdc0 (00000000 00000000)
+        nand 000f423f, ffffffff => fff0bdc0 (00000000 00000000)
+        nand ffffffff, 00000000 => ffffffff (00000000 00000000)
+        nand ffffffff, 000f423f => fff0bdc0 (00000000 00000000)
+        nand ffffffff, ffffffff => 00000000 (00000000 00000000)
+
+         nor 00000000, 00000000 => ffffffff (00000000 00000000)
+         nor 00000000, 000f423f => fff0bdc0 (00000000 00000000)
+         nor 00000000, ffffffff => 00000000 (00000000 00000000)
+         nor 000f423f, 00000000 => fff0bdc0 (00000000 00000000)
+         nor 000f423f, 000f423f => fff0bdc0 (00000000 00000000)
+         nor 000f423f, ffffffff => 00000000 (00000000 00000000)
+         nor ffffffff, 00000000 => 00000000 (00000000 00000000)
+         nor ffffffff, 000f423f => 00000000 (00000000 00000000)
+         nor ffffffff, ffffffff => 00000000 (00000000 00000000)
+
+          or 00000000, 00000000 => 00000000 (00000000 00000000)
+          or 00000000, 000f423f => 000f423f (00000000 00000000)
+          or 00000000, ffffffff => ffffffff (00000000 00000000)
+          or 000f423f, 00000000 => 000f423f (00000000 00000000)
+          or 000f423f, 000f423f => 000f423f (00000000 00000000)
+          or 000f423f, ffffffff => ffffffff (00000000 00000000)
+          or ffffffff, 00000000 => ffffffff (00000000 00000000)
+          or ffffffff, 000f423f => ffffffff (00000000 00000000)
+          or ffffffff, ffffffff => ffffffff (00000000 00000000)
+
+         orc 00000000, 00000000 => ffffffff (00000000 00000000)
+         orc 00000000, 000f423f => fff0bdc0 (00000000 00000000)
+         orc 00000000, ffffffff => 00000000 (00000000 00000000)
+         orc 000f423f, 00000000 => ffffffff (00000000 00000000)
+         orc 000f423f, 000f423f => ffffffff (00000000 00000000)
+         orc 000f423f, ffffffff => 000f423f (00000000 00000000)
+         orc ffffffff, 00000000 => ffffffff (00000000 00000000)
+         orc ffffffff, 000f423f => ffffffff (00000000 00000000)
+         orc ffffffff, ffffffff => ffffffff (00000000 00000000)
+
+         xor 00000000, 00000000 => 00000000 (00000000 00000000)
+         xor 00000000, 000f423f => 000f423f (00000000 00000000)
+         xor 00000000, ffffffff => ffffffff (00000000 00000000)
+         xor 000f423f, 00000000 => 000f423f (00000000 00000000)
+         xor 000f423f, 000f423f => 00000000 (00000000 00000000)
+         xor 000f423f, ffffffff => fff0bdc0 (00000000 00000000)
+         xor ffffffff, 00000000 => ffffffff (00000000 00000000)
+         xor ffffffff, 000f423f => fff0bdc0 (00000000 00000000)
+         xor ffffffff, ffffffff => 00000000 (00000000 00000000)
+
+         slw 00000000, 00000000 => 00000000 (00000000 00000000)
+         slw 00000000, 000f423f => 00000000 (00000000 00000000)
+         slw 00000000, ffffffff => 00000000 (00000000 00000000)
+         slw 000f423f, 00000000 => 000f423f (00000000 00000000)
+         slw 000f423f, 000f423f => 00000000 (00000000 00000000)
+         slw 000f423f, ffffffff => 00000000 (00000000 00000000)
+         slw ffffffff, 00000000 => ffffffff (00000000 00000000)
+         slw ffffffff, 000f423f => 00000000 (00000000 00000000)
+         slw ffffffff, ffffffff => 00000000 (00000000 00000000)
+
+        sraw 00000000, 00000000 => 00000000 (00000000 00000000)
+        sraw 00000000, 000f423f => 00000000 (00000000 00000000)
+        sraw 00000000, ffffffff => 00000000 (00000000 00000000)
+        sraw 000f423f, 00000000 => 000f423f (00000000 00000000)
+        sraw 000f423f, 000f423f => 00000000 (00000000 00000000)
+        sraw 000f423f, ffffffff => 00000000 (00000000 00000000)
+        sraw ffffffff, 00000000 => ffffffff (00000000 00000000)
+        sraw ffffffff, 000f423f => ffffffff (00000000 20000000)
+        sraw ffffffff, ffffffff => ffffffff (00000000 20000000)
+
+         srw 00000000, 00000000 => 00000000 (00000000 00000000)
+         srw 00000000, 000f423f => 00000000 (00000000 00000000)
+         srw 00000000, ffffffff => 00000000 (00000000 00000000)
+         srw 000f423f, 00000000 => 000f423f (00000000 00000000)
+         srw 000f423f, 000f423f => 00000000 (00000000 00000000)
+         srw 000f423f, ffffffff => 00000000 (00000000 00000000)
+         srw ffffffff, 00000000 => ffffffff (00000000 00000000)
+         srw ffffffff, 000f423f => 00000000 (00000000 00000000)
+         srw ffffffff, ffffffff => 00000000 (00000000 00000000)
+
+PPC integer logical insns with two args with flags update:
+        and. 00000000, 00000000 => 00000000 (20000000 00000000)
+        and. 00000000, 000f423f => 00000000 (20000000 00000000)
+        and. 00000000, ffffffff => 00000000 (20000000 00000000)
+        and. 000f423f, 00000000 => 00000000 (20000000 00000000)
+        and. 000f423f, 000f423f => 000f423f (40000000 00000000)
+        and. 000f423f, ffffffff => 000f423f (40000000 00000000)
+        and. ffffffff, 00000000 => 00000000 (20000000 00000000)
+        and. ffffffff, 000f423f => 000f423f (40000000 00000000)
+        and. ffffffff, ffffffff => ffffffff (80000000 00000000)
+
+       andc. 00000000, 00000000 => 00000000 (20000000 00000000)
+       andc. 00000000, 000f423f => 00000000 (20000000 00000000)
+       andc. 00000000, ffffffff => 00000000 (20000000 00000000)
+       andc. 000f423f, 00000000 => 000f423f (40000000 00000000)
+       andc. 000f423f, 000f423f => 00000000 (20000000 00000000)
+       andc. 000f423f, ffffffff => 00000000 (20000000 00000000)
+       andc. ffffffff, 00000000 => ffffffff (80000000 00000000)
+       andc. ffffffff, 000f423f => fff0bdc0 (80000000 00000000)
+       andc. ffffffff, ffffffff => 00000000 (20000000 00000000)
+
+        eqv. 00000000, 00000000 => ffffffff (80000000 00000000)
+        eqv. 00000000, 000f423f => fff0bdc0 (80000000 00000000)
+        eqv. 00000000, ffffffff => 00000000 (20000000 00000000)
+        eqv. 000f423f, 00000000 => fff0bdc0 (80000000 00000000)
+        eqv. 000f423f, 000f423f => ffffffff (80000000 00000000)
+        eqv. 000f423f, ffffffff => 000f423f (40000000 00000000)
+        eqv. ffffffff, 00000000 => 00000000 (20000000 00000000)
+        eqv. ffffffff, 000f423f => 000f423f (40000000 00000000)
+        eqv. ffffffff, ffffffff => ffffffff (80000000 00000000)
+
+       nand. 00000000, 00000000 => ffffffff (80000000 00000000)
+       nand. 00000000, 000f423f => ffffffff (80000000 00000000)
+       nand. 00000000, ffffffff => ffffffff (80000000 00000000)
+       nand. 000f423f, 00000000 => ffffffff (80000000 00000000)
+       nand. 000f423f, 000f423f => fff0bdc0 (80000000 00000000)
+       nand. 000f423f, ffffffff => fff0bdc0 (80000000 00000000)
+       nand. ffffffff, 00000000 => ffffffff (80000000 00000000)
+       nand. ffffffff, 000f423f => fff0bdc0 (80000000 00000000)
+       nand. ffffffff, ffffffff => 00000000 (20000000 00000000)
+
+        nor. 00000000, 00000000 => ffffffff (80000000 00000000)
+        nor. 00000000, 000f423f => fff0bdc0 (80000000 00000000)
+        nor. 00000000, ffffffff => 00000000 (20000000 00000000)
+        nor. 000f423f, 00000000 => fff0bdc0 (80000000 00000000)
+        nor. 000f423f, 000f423f => fff0bdc0 (80000000 00000000)
+        nor. 000f423f, ffffffff => 00000000 (20000000 00000000)
+        nor. ffffffff, 00000000 => 00000000 (20000000 00000000)
+        nor. ffffffff, 000f423f => 00000000 (20000000 00000000)
+        nor. ffffffff, ffffffff => 00000000 (20000000 00000000)
+
+         or. 00000000, 00000000 => 00000000 (20000000 00000000)
+         or. 00000000, 000f423f => 000f423f (40000000 00000000)
+         or. 00000000, ffffffff => ffffffff (80000000 00000000)
+         or. 000f423f, 00000000 => 000f423f (40000000 00000000)
+         or. 000f423f, 000f423f => 000f423f (40000000 00000000)
+         or. 000f423f, ffffffff => ffffffff (80000000 00000000)
+         or. ffffffff, 00000000 => ffffffff (80000000 00000000)
+         or. ffffffff, 000f423f => ffffffff (80000000 00000000)
+         or. ffffffff, ffffffff => ffffffff (80000000 00000000)
+
+        orc. 00000000, 00000000 => ffffffff (80000000 00000000)
+        orc. 00000000, 000f423f => fff0bdc0 (80000000 00000000)
+        orc. 00000000, ffffffff => 00000000 (20000000 00000000)
+        orc. 000f423f, 00000000 => ffffffff (80000000 00000000)
+        orc. 000f423f, 000f423f => ffffffff (80000000 00000000)
+        orc. 000f423f, ffffffff => 000f423f (40000000 00000000)
+        orc. ffffffff, 00000000 => ffffffff (80000000 00000000)
+        orc. ffffffff, 000f423f => ffffffff (80000000 00000000)
+        orc. ffffffff, ffffffff => ffffffff (80000000 00000000)
+
+        xor. 00000000, 00000000 => 00000000 (20000000 00000000)
+        xor. 00000000, 000f423f => 000f423f (40000000 00000000)
+        xor. 00000000, ffffffff => ffffffff (80000000 00000000)
+        xor. 000f423f, 00000000 => 000f423f (40000000 00000000)
+        xor. 000f423f, 000f423f => 00000000 (20000000 00000000)
+        xor. 000f423f, ffffffff => fff0bdc0 (80000000 00000000)
+        xor. ffffffff, 00000000 => ffffffff (80000000 00000000)
+        xor. ffffffff, 000f423f => fff0bdc0 (80000000 00000000)
+        xor. ffffffff, ffffffff => 00000000 (20000000 00000000)
+
+        slw. 00000000, 00000000 => 00000000 (20000000 00000000)
+        slw. 00000000, 000f423f => 00000000 (20000000 00000000)
+        slw. 00000000, ffffffff => 00000000 (20000000 00000000)
+        slw. 000f423f, 00000000 => 000f423f (40000000 00000000)
+        slw. 000f423f, 000f423f => 00000000 (20000000 00000000)
+        slw. 000f423f, ffffffff => 00000000 (20000000 00000000)
+        slw. ffffffff, 00000000 => ffffffff (80000000 00000000)
+        slw. ffffffff, 000f423f => 00000000 (20000000 00000000)
+        slw. ffffffff, ffffffff => 00000000 (20000000 00000000)
+
+       sraw. 00000000, 00000000 => 00000000 (20000000 00000000)
+       sraw. 00000000, 000f423f => 00000000 (20000000 00000000)
+       sraw. 00000000, ffffffff => 00000000 (20000000 00000000)
+       sraw. 000f423f, 00000000 => 000f423f (40000000 00000000)
+       sraw. 000f423f, 000f423f => 00000000 (20000000 00000000)
+       sraw. 000f423f, ffffffff => 00000000 (20000000 00000000)
+       sraw. ffffffff, 00000000 => ffffffff (80000000 00000000)
+       sraw. ffffffff, 000f423f => ffffffff (80000000 20000000)
+       sraw. ffffffff, ffffffff => ffffffff (80000000 20000000)
+
+        srw. 00000000, 00000000 => 00000000 (20000000 00000000)
+        srw. 00000000, 000f423f => 00000000 (20000000 00000000)
+        srw. 00000000, ffffffff => 00000000 (20000000 00000000)
+        srw. 000f423f, 00000000 => 000f423f (40000000 00000000)
+        srw. 000f423f, 000f423f => 00000000 (20000000 00000000)
+        srw. 000f423f, ffffffff => 00000000 (20000000 00000000)
+        srw. ffffffff, 00000000 => ffffffff (80000000 00000000)
+        srw. ffffffff, 000f423f => 00000000 (20000000 00000000)
+        srw. ffffffff, ffffffff => 00000000 (20000000 00000000)
+
+PPC integer compare insns (two args):
+        cmpw 00000000, 00000000 => 00000000 (00200000 00000000)
+        cmpw 00000000, 000f423f => 00000000 (00800000 00000000)
+        cmpw 00000000, ffffffff => 00000000 (00400000 00000000)
+        cmpw 000f423f, 00000000 => 00000000 (00400000 00000000)
+        cmpw 000f423f, 000f423f => 00000000 (00200000 00000000)
+        cmpw 000f423f, ffffffff => 00000000 (00400000 00000000)
+        cmpw ffffffff, 00000000 => 00000000 (00800000 00000000)
+        cmpw ffffffff, 000f423f => 00000000 (00800000 00000000)
+        cmpw ffffffff, ffffffff => 00000000 (00200000 00000000)
+
+       cmplw 00000000, 00000000 => 00000000 (00200000 00000000)
+       cmplw 00000000, 000f423f => 00000000 (00800000 00000000)
+       cmplw 00000000, ffffffff => 00000000 (00800000 00000000)
+       cmplw 000f423f, 00000000 => 00000000 (00400000 00000000)
+       cmplw 000f423f, 000f423f => 00000000 (00200000 00000000)
+       cmplw 000f423f, ffffffff => 00000000 (00800000 00000000)
+       cmplw ffffffff, 00000000 => 00000000 (00400000 00000000)
+       cmplw ffffffff, 000f423f => 00000000 (00400000 00000000)
+       cmplw ffffffff, ffffffff => 00000000 (00200000 00000000)
+
+PPC integer compare with immediate insns (two args):
+       cmpwi 00000000, 00000000 => 00000000 (00200000 00000000)
+       cmpwi 00000000, 000003e7 => 00000000 (00800000 00000000)
+       cmpwi 00000000, 0000ffff => 00000000 (00400000 00000000)
+       cmpwi 000f423f, 00000000 => 00000000 (00400000 00000000)
+       cmpwi 000f423f, 000003e7 => 00000000 (00400000 00000000)
+       cmpwi 000f423f, 0000ffff => 00000000 (00400000 00000000)
+       cmpwi ffffffff, 00000000 => 00000000 (00800000 00000000)
+       cmpwi ffffffff, 000003e7 => 00000000 (00800000 00000000)
+       cmpwi ffffffff, 0000ffff => 00000000 (00200000 00000000)
+
+      cmplwi 00000000, 00000000 => 00000000 (00200000 00000000)
+      cmplwi 00000000, 000003e7 => 00000000 (00800000 00000000)
+      cmplwi 00000000, 0000ffff => 00000000 (00800000 00000000)
+      cmplwi 000f423f, 00000000 => 00000000 (00400000 00000000)
+      cmplwi 000f423f, 000003e7 => 00000000 (00400000 00000000)
+      cmplwi 000f423f, 0000ffff => 00000000 (00400000 00000000)
+      cmplwi ffffffff, 00000000 => 00000000 (00400000 00000000)
+      cmplwi ffffffff, 000003e7 => 00000000 (00400000 00000000)
+      cmplwi ffffffff, 0000ffff => 00000000 (00400000 00000000)
+
+PPC integer logical insns
+    with one register + one 16 bits immediate args:
+         ori 00000000, 00000000 => 00000000 (00000000 00000000)
+         ori 00000000, 000003e7 => 000003e7 (00000000 00000000)
+         ori 00000000, 0000ffff => 0000ffff (00000000 00000000)
+         ori 000f423f, 00000000 => 000f423f (00000000 00000000)
+         ori 000f423f, 000003e7 => 000f43ff (00000000 00000000)
+         ori 000f423f, 0000ffff => 000fffff (00000000 00000000)
+         ori ffffffff, 00000000 => ffffffff (00000000 00000000)
+         ori ffffffff, 000003e7 => ffffffff (00000000 00000000)
+         ori ffffffff, 0000ffff => ffffffff (00000000 00000000)
+
+        oris 00000000, 00000000 => 00000000 (00000000 00000000)
+        oris 00000000, 000003e7 => 03e70000 (00000000 00000000)
+        oris 00000000, 0000ffff => ffff0000 (00000000 00000000)
+        oris 000f423f, 00000000 => 000f423f (00000000 00000000)
+        oris 000f423f, 000003e7 => 03ef423f (00000000 00000000)
+        oris 000f423f, 0000ffff => ffff423f (00000000 00000000)
+        oris ffffffff, 00000000 => ffffffff (00000000 00000000)
+        oris ffffffff, 000003e7 => ffffffff (00000000 00000000)
+        oris ffffffff, 0000ffff => ffffffff (00000000 00000000)
+
+        xori 00000000, 00000000 => 00000000 (00000000 00000000)
+        xori 00000000, 000003e7 => 000003e7 (00000000 00000000)
+        xori 00000000, 0000ffff => 0000ffff (00000000 00000000)
+        xori 000f423f, 00000000 => 000f423f (00000000 00000000)
+        xori 000f423f, 000003e7 => 000f41d8 (00000000 00000000)
+        xori 000f423f, 0000ffff => 000fbdc0 (00000000 00000000)
+        xori ffffffff, 00000000 => ffffffff (00000000 00000000)
+        xori ffffffff, 000003e7 => fffffc18 (00000000 00000000)
+        xori ffffffff, 0000ffff => ffff0000 (00000000 00000000)
+
+       xoris 00000000, 00000000 => 00000000 (00000000 00000000)
+       xoris 00000000, 000003e7 => 03e70000 (00000000 00000000)
+       xoris 00000000, 0000ffff => ffff0000 (00000000 00000000)
+       xoris 000f423f, 00000000 => 000f423f (00000000 00000000)
+       xoris 000f423f, 000003e7 => 03e8423f (00000000 00000000)
+       xoris 000f423f, 0000ffff => fff0423f (00000000 00000000)
+       xoris ffffffff, 00000000 => ffffffff (00000000 00000000)
+       xoris ffffffff, 000003e7 => fc18ffff (00000000 00000000)
+       xoris ffffffff, 0000ffff => 0000ffff (00000000 00000000)
+
+PPC integer logical insns
+    with one register + one 16 bits immediate args with flags update:
+       andi. 00000000, 00000000 => 00000000 (20000000 00000000)
+       andi. 00000000, 000003e7 => 00000000 (20000000 00000000)
+       andi. 00000000, 0000ffff => 00000000 (20000000 00000000)
+       andi. 000f423f, 00000000 => 00000000 (20000000 00000000)
+       andi. 000f423f, 000003e7 => 00000227 (40000000 00000000)
+       andi. 000f423f, 0000ffff => 0000423f (40000000 00000000)
+       andi. ffffffff, 00000000 => 00000000 (20000000 00000000)
+       andi. ffffffff, 000003e7 => 000003e7 (40000000 00000000)
+       andi. ffffffff, 0000ffff => 0000ffff (40000000 00000000)
+
+      andis. 00000000, 00000000 => 00000000 (20000000 00000000)
+      andis. 00000000, 000003e7 => 00000000 (20000000 00000000)
+      andis. 00000000, 0000ffff => 00000000 (20000000 00000000)
+      andis. 000f423f, 00000000 => 00000000 (20000000 00000000)
+      andis. 000f423f, 000003e7 => 00070000 (40000000 00000000)
+      andis. 000f423f, 0000ffff => 000f0000 (40000000 00000000)
+      andis. ffffffff, 00000000 => 00000000 (20000000 00000000)
+      andis. ffffffff, 000003e7 => 03e70000 (40000000 00000000)
+      andis. ffffffff, 0000ffff => ffff0000 (80000000 00000000)
+
+PPC condition register logical insns - two operands:
+       crand 00000000, 00000000 => ffff0000 (00000000 00000000)
+       crand 00000000, 000f423f => ffff0000 (00000000 00000000)
+       crand 00000000, ffffffff => ffff0000 (00000000 00000000)
+       crand 000f423f, 00000000 => ffff0000 (00000000 00000000)
+       crand 000f423f, 000f423f => ffff0000 (00000000 00000000)
+       crand 000f423f, ffffffff => ffff0000 (00000000 00000000)
+       crand ffffffff, 00000000 => ffff0000 (00000000 00000000)
+       crand ffffffff, 000f423f => ffff0000 (00000000 00000000)
+       crand ffffffff, ffffffff => ffff0000 (00000000 00000000)
+
+      crandc 00000000, 00000000 => ffff0000 (00000000 00000000)
+      crandc 00000000, 000f423f => ffff0000 (00000000 00000000)
+      crandc 00000000, ffffffff => ffff0000 (00000000 00000000)
+      crandc 000f423f, 00000000 => ffff0000 (00000000 00000000)
+      crandc 000f423f, 000f423f => ffff0000 (00000000 00000000)
+      crandc 000f423f, ffffffff => ffff0000 (00000000 00000000)
+      crandc ffffffff, 00000000 => ffff0000 (00000000 00000000)
+      crandc ffffffff, 000f423f => ffff0000 (00000000 00000000)
+      crandc ffffffff, ffffffff => ffff0000 (00000000 00000000)
+
+       creqv 00000000, 00000000 => ffff0000 (00004000 00000000)
+       creqv 00000000, 000f423f => ffff0000 (00004000 00000000)
+       creqv 00000000, ffffffff => ffff0000 (00004000 00000000)
+       creqv 000f423f, 00000000 => ffff0000 (00004000 00000000)
+       creqv 000f423f, 000f423f => ffff0000 (00004000 00000000)
+       creqv 000f423f, ffffffff => ffff0000 (00004000 00000000)
+       creqv ffffffff, 00000000 => ffff0000 (00004000 00000000)
+       creqv ffffffff, 000f423f => ffff0000 (00004000 00000000)
+       creqv ffffffff, ffffffff => ffff0000 (00004000 00000000)
+
+      crnand 00000000, 00000000 => ffff0000 (00004000 00000000)
+      crnand 00000000, 000f423f => ffff0000 (00004000 00000000)
+      crnand 00000000, ffffffff => ffff0000 (00004000 00000000)
+      crnand 000f423f, 00000000 => ffff0000 (00004000 00000000)
+      crnand 000f423f, 000f423f => ffff0000 (00004000 00000000)
+      crnand 000f423f, ffffffff => ffff0000 (00004000 00000000)
+      crnand ffffffff, 00000000 => ffff0000 (00004000 00000000)
+      crnand ffffffff, 000f423f => ffff0000 (00004000 00000000)
+      crnand ffffffff, ffffffff => ffff0000 (00004000 00000000)
+
+       crnor 00000000, 00000000 => ffff0000 (00004000 00000000)
+       crnor 00000000, 000f423f => ffff0000 (00004000 00000000)
+       crnor 00000000, ffffffff => ffff0000 (00004000 00000000)
+       crnor 000f423f, 00000000 => ffff0000 (00004000 00000000)
+       crnor 000f423f, 000f423f => ffff0000 (00004000 00000000)
+       crnor 000f423f, ffffffff => ffff0000 (00004000 00000000)
+       crnor ffffffff, 00000000 => ffff0000 (00004000 00000000)
+       crnor ffffffff, 000f423f => ffff0000 (00004000 00000000)
+       crnor ffffffff, ffffffff => ffff0000 (00004000 00000000)
+
+        cror 00000000, 00000000 => ffff0000 (00000000 00000000)
+        cror 00000000, 000f423f => ffff0000 (00000000 00000000)
+        cror 00000000, ffffffff => ffff0000 (00000000 00000000)
+        cror 000f423f, 00000000 => ffff0000 (00000000 00000000)
+        cror 000f423f, 000f423f => ffff0000 (00000000 00000000)
+        cror 000f423f, ffffffff => ffff0000 (00000000 00000000)
+        cror ffffffff, 00000000 => ffff0000 (00000000 00000000)
+        cror ffffffff, 000f423f => ffff0000 (00000000 00000000)
+        cror ffffffff, ffffffff => ffff0000 (00000000 00000000)
+
+       crorc 00000000, 00000000 => ffff0000 (00004000 00000000)
+       crorc 00000000, 000f423f => ffff0000 (00004000 00000000)
+       crorc 00000000, ffffffff => ffff0000 (00004000 00000000)
+       crorc 000f423f, 00000000 => ffff0000 (00004000 00000000)
+       crorc 000f423f, 000f423f => ffff0000 (00004000 00000000)
+       crorc 000f423f, ffffffff => ffff0000 (00004000 00000000)
+       crorc ffffffff, 00000000 => ffff0000 (00004000 00000000)
+       crorc ffffffff, 000f423f => ffff0000 (00004000 00000000)
+       crorc ffffffff, ffffffff => ffff0000 (00004000 00000000)
+
+       crxor 00000000, 00000000 => ffff0000 (00000000 00000000)
+       crxor 00000000, 000f423f => ffff0000 (00000000 00000000)
+       crxor 00000000, ffffffff => ffff0000 (00000000 00000000)
+       crxor 000f423f, 00000000 => ffff0000 (00000000 00000000)
+       crxor 000f423f, 000f423f => ffff0000 (00000000 00000000)
+       crxor 000f423f, ffffffff => ffff0000 (00000000 00000000)
+       crxor ffffffff, 00000000 => ffff0000 (00000000 00000000)
+       crxor ffffffff, 000f423f => ffff0000 (00000000 00000000)
+       crxor ffffffff, ffffffff => ffff0000 (00000000 00000000)
+
+PPC integer logical insns with one arg:
+      cntlzw 00000000 => 00000020 (00000000 00000000)
+      cntlzw 000f423f => 0000000c (00000000 00000000)
+      cntlzw ffffffff => 00000000 (00000000 00000000)
+
+       extsb 00000000 => 00000000 (00000000 00000000)
+       extsb 000f423f => 0000003f (00000000 00000000)
+       extsb ffffffff => ffffffff (00000000 00000000)
+
+       extsh 00000000 => 00000000 (00000000 00000000)
+       extsh 000f423f => 0000423f (00000000 00000000)
+       extsh ffffffff => ffffffff (00000000 00000000)
+
+         neg 00000000 => 00000000 (00000000 00000000)
+         neg 000f423f => fff0bdc1 (00000000 00000000)
+         neg ffffffff => 00000001 (00000000 00000000)
+
+        nego 00000000 => 00000000 (00000000 00000000)
+        nego 000f423f => fff0bdc1 (00000000 00000000)
+        nego ffffffff => 00000001 (00000000 00000000)
+
+PPC integer logical insns with one arg with flags update:
+     cntlzw. 00000000 => 00000020 (40000000 00000000)
+     cntlzw. 000f423f => 0000000c (40000000 00000000)
+     cntlzw. ffffffff => 00000000 (20000000 00000000)
+
+      extsb. 00000000 => 00000000 (20000000 00000000)
+      extsb. 000f423f => 0000003f (40000000 00000000)
+      extsb. ffffffff => ffffffff (80000000 00000000)
+
+      extsh. 00000000 => 00000000 (20000000 00000000)
+      extsh. 000f423f => 0000423f (40000000 00000000)
+      extsh. ffffffff => ffffffff (80000000 00000000)
+
+        neg. 00000000 => 00000000 (20000000 00000000)
+        neg. 000f423f => fff0bdc1 (80000000 00000000)
+        neg. ffffffff => 00000001 (40000000 00000000)
+
+       nego. 00000000 => 00000000 (20000000 00000000)
+       nego. 000f423f => fff0bdc1 (80000000 00000000)
+       nego. ffffffff => 00000001 (40000000 00000000)
+
+PPC logical insns with special forms:
+      rlwimi 00000000,  0,  0,  0 => 00000000 (00000000 00000000)
+      rlwimi 00000000,  0,  0, 31 => 00000000 (00000000 00000000)
+      rlwimi 00000000,  0, 31,  0 => 00000000 (00000000 00000000)
+      rlwimi 00000000,  0, 31, 31 => 00000000 (00000000 00000000)
+      rlwimi 00000000, 31,  0,  0 => 00000000 (00000000 00000000)
+      rlwimi 00000000, 31,  0, 31 => 00000000 (00000000 00000000)
+      rlwimi 00000000, 31, 31,  0 => 00000000 (00000000 00000000)
+      rlwimi 00000000, 31, 31, 31 => 00000000 (00000000 00000000)
+      rlwimi 000f423f,  0,  0,  0 => 00000000 (00000000 00000000)
+      rlwimi 000f423f,  0,  0, 31 => 000f423f (00000000 00000000)
+      rlwimi 000f423f,  0, 31,  0 => 000f423f (00000000 00000000)
+      rlwimi 000f423f,  0, 31, 31 => 000f423f (00000000 00000000)
+      rlwimi 000f423f, 31,  0,  0 => 800f423f (00000000 00000000)
+      rlwimi 000f423f, 31,  0, 31 => 8007a11f (00000000 00000000)
+      rlwimi 000f423f, 31, 31,  0 => 8007a11f (00000000 00000000)
+      rlwimi 000f423f, 31, 31, 31 => 8007a11f (00000000 00000000)
+      rlwimi ffffffff,  0,  0,  0 => 8007a11f (00000000 00000000)
+      rlwimi ffffffff,  0,  0, 31 => ffffffff (00000000 00000000)
+      rlwimi ffffffff,  0, 31,  0 => ffffffff (00000000 00000000)
+      rlwimi ffffffff,  0, 31, 31 => ffffffff (00000000 00000000)
+      rlwimi ffffffff, 31,  0,  0 => ffffffff (00000000 00000000)
+      rlwimi ffffffff, 31,  0, 31 => ffffffff (00000000 00000000)
+      rlwimi ffffffff, 31, 31,  0 => ffffffff (00000000 00000000)
+      rlwimi ffffffff, 31, 31, 31 => ffffffff (00000000 00000000)
+
+      rlwinm 00000000,  0,  0,  0 => 00000000 (00000000 00000000)
+      rlwinm 00000000,  0,  0, 31 => 00000000 (00000000 00000000)
+      rlwinm 00000000,  0, 31,  0 => 00000000 (00000000 00000000)
+      rlwinm 00000000,  0, 31, 31 => 00000000 (00000000 00000000)
+      rlwinm 00000000, 31,  0,  0 => 00000000 (00000000 00000000)
+      rlwinm 00000000, 31,  0, 31 => 00000000 (00000000 00000000)
+      rlwinm 00000000, 31, 31,  0 => 00000000 (00000000 00000000)
+      rlwinm 00000000, 31, 31, 31 => 00000000 (00000000 00000000)
+      rlwinm 000f423f,  0,  0,  0 => 00000000 (00000000 00000000)
+      rlwinm 000f423f,  0,  0, 31 => 000f423f (00000000 00000000)
+      rlwinm 000f423f,  0, 31,  0 => 00000001 (00000000 00000000)
+      rlwinm 000f423f,  0, 31, 31 => 00000001 (00000000 00000000)
+      rlwinm 000f423f, 31,  0,  0 => 80000000 (00000000 00000000)
+      rlwinm 000f423f, 31,  0, 31 => 8007a11f (00000000 00000000)
+      rlwinm 000f423f, 31, 31,  0 => 80000001 (00000000 00000000)
+      rlwinm 000f423f, 31, 31, 31 => 00000001 (00000000 00000000)
+      rlwinm ffffffff,  0,  0,  0 => 80000000 (00000000 00000000)
+      rlwinm ffffffff,  0,  0, 31 => ffffffff (00000000 00000000)
+      rlwinm ffffffff,  0, 31,  0 => 80000001 (00000000 00000000)
+      rlwinm ffffffff,  0, 31, 31 => 00000001 (00000000 00000000)
+      rlwinm ffffffff, 31,  0,  0 => 80000000 (00000000 00000000)
+      rlwinm ffffffff, 31,  0, 31 => ffffffff (00000000 00000000)
+      rlwinm ffffffff, 31, 31,  0 => 80000001 (00000000 00000000)
+      rlwinm ffffffff, 31, 31, 31 => 00000001 (00000000 00000000)
+
+       rlwnm 00000000, 00000000,  0,  0 => 00000000 (00000000 00000000)
+       rlwnm 00000000, 00000000,  0, 31 => 00000000 (00000000 00000000)
+       rlwnm 00000000, 00000000, 31,  0 => 00000000 (00000000 00000000)
+       rlwnm 00000000, 00000000, 31, 31 => 00000000 (00000000 00000000)
+       rlwnm 00000000, 000f423f,  0,  0 => 00000000 (00000000 00000000)
+       rlwnm 00000000, 000f423f,  0, 31 => 00000000 (00000000 00000000)
+       rlwnm 00000000, 000f423f, 31,  0 => 00000000 (00000000 00000000)
+       rlwnm 00000000, 000f423f, 31, 31 => 00000000 (00000000 00000000)
+       rlwnm 00000000, ffffffff,  0,  0 => 00000000 (00000000 00000000)
+       rlwnm 00000000, ffffffff,  0, 31 => 00000000 (00000000 00000000)
+       rlwnm 00000000, ffffffff, 31,  0 => 00000000 (00000000 00000000)
+       rlwnm 00000000, ffffffff, 31, 31 => 00000000 (00000000 00000000)
+       rlwnm 000f423f, 00000000,  0,  0 => 00000000 (00000000 00000000)
+       rlwnm 000f423f, 00000000,  0, 31 => 000f423f (00000000 00000000)
+       rlwnm 000f423f, 00000000, 31,  0 => 00000001 (00000000 00000000)
+       rlwnm 000f423f, 00000000, 31, 31 => 00000001 (00000000 00000000)
+       rlwnm 000f423f, 000f423f,  0,  0 => 80000000 (00000000 00000000)
+       rlwnm 000f423f, 000f423f,  0, 31 => 8007a11f (00000000 00000000)
+       rlwnm 000f423f, 000f423f, 31,  0 => 80000001 (00000000 00000000)
+       rlwnm 000f423f, 000f423f, 31, 31 => 00000001 (00000000 00000000)
+       rlwnm 000f423f, ffffffff,  0,  0 => 80000000 (00000000 00000000)
+       rlwnm 000f423f, ffffffff,  0, 31 => 8007a11f (00000000 00000000)
+       rlwnm 000f423f, ffffffff, 31,  0 => 80000001 (00000000 00000000)
+       rlwnm 000f423f, ffffffff, 31, 31 => 00000001 (00000000 00000000)
+       rlwnm ffffffff, 00000000,  0,  0 => 80000000 (00000000 00000000)
+       rlwnm ffffffff, 00000000,  0, 31 => ffffffff (00000000 00000000)
+       rlwnm ffffffff, 00000000, 31,  0 => 80000001 (00000000 00000000)
+       rlwnm ffffffff, 00000000, 31, 31 => 00000001 (00000000 00000000)
+       rlwnm ffffffff, 000f423f,  0,  0 => 80000000 (00000000 00000000)
+       rlwnm ffffffff, 000f423f,  0, 31 => ffffffff (00000000 00000000)
+       rlwnm ffffffff, 000f423f, 31,  0 => 80000001 (00000000 00000000)
+       rlwnm ffffffff, 000f423f, 31, 31 => 00000001 (00000000 00000000)
+       rlwnm ffffffff, ffffffff,  0,  0 => 80000000 (00000000 00000000)
+       rlwnm ffffffff, ffffffff,  0, 31 => ffffffff (00000000 00000000)
+       rlwnm ffffffff, ffffffff, 31,  0 => 80000001 (00000000 00000000)
+       rlwnm ffffffff, ffffffff, 31, 31 => 00000001 (00000000 00000000)
+
+       srawi 00000000,  0 => 00000000 (00000000 00000000)
+       srawi 00000000, 31 => 00000000 (00000000 00000000)
+       srawi 000f423f,  0 => 000f423f (00000000 00000000)
+       srawi 000f423f, 31 => 00000000 (00000000 00000000)
+       srawi ffffffff,  0 => ffffffff (00000000 00000000)
+       srawi ffffffff, 31 => ffffffff (00000000 20000000)
+
+        mfcr (00000000) => 00000000 (00000000 00000000)
+        mfcr (000f423f) => 000f423f (000f423f 00000000)
+        mfcr (ffffffff) => ffffffff (ffffffff 00000000)
+
+       mfspr 1 (00000000) -> mtxer -> mfxer => 00000000
+       mfspr 1 (000f423f) -> mtxer -> mfxer => 0000003f
+       mfspr 1 (ffffffff) -> mtxer -> mfxer => e000007f
+       mfspr 8 (00000000) ->  mtlr ->  mflr => 00000000
+       mfspr 8 (000f423f) ->  mtlr ->  mflr => 000f423f
+       mfspr 8 (ffffffff) ->  mtlr ->  mflr => ffffffff
+       mfspr 9 (00000000) -> mtctr -> mfctr => 00000000
+       mfspr 9 (000f423f) -> mtctr -> mfctr => 000f423f
+       mfspr 9 (ffffffff) -> mtctr -> mfctr => ffffffff
+
+
+PPC logical insns with special forms with flags update:
+     rlwimi. 00000000,  0,  0,  0 => 00000000 (20000000 00000000)
+     rlwimi. 00000000,  0,  0, 31 => 00000000 (20000000 00000000)
+     rlwimi. 00000000,  0, 31,  0 => 00000000 (20000000 00000000)
+     rlwimi. 00000000,  0, 31, 31 => 00000000 (20000000 00000000)
+     rlwimi. 00000000, 31,  0,  0 => 00000000 (20000000 00000000)
+     rlwimi. 00000000, 31,  0, 31 => 00000000 (20000000 00000000)
+     rlwimi. 00000000, 31, 31,  0 => 00000000 (20000000 00000000)
+     rlwimi. 00000000, 31, 31, 31 => 00000000 (20000000 00000000)
+     rlwimi. 000f423f,  0,  0,  0 => 00000000 (20000000 00000000)
+     rlwimi. 000f423f,  0,  0, 31 => 000f423f (40000000 00000000)
+     rlwimi. 000f423f,  0, 31,  0 => 000f423f (40000000 00000000)
+     rlwimi. 000f423f,  0, 31, 31 => 000f423f (40000000 00000000)
+     rlwimi. 000f423f, 31,  0,  0 => 800f423f (80000000 00000000)
+     rlwimi. 000f423f, 31,  0, 31 => 8007a11f (80000000 00000000)
+     rlwimi. 000f423f, 31, 31,  0 => 8007a11f (80000000 00000000)
+     rlwimi. 000f423f, 31, 31, 31 => 8007a11f (80000000 00000000)
+     rlwimi. ffffffff,  0,  0,  0 => 8007a11f (80000000 00000000)
+     rlwimi. ffffffff,  0,  0, 31 => ffffffff (80000000 00000000)
+     rlwimi. ffffffff,  0, 31,  0 => ffffffff (80000000 00000000)
+     rlwimi. ffffffff,  0, 31, 31 => ffffffff (80000000 00000000)
+     rlwimi. ffffffff, 31,  0,  0 => ffffffff (80000000 00000000)
+     rlwimi. ffffffff, 31,  0, 31 => ffffffff (80000000 00000000)
+     rlwimi. ffffffff, 31, 31,  0 => ffffffff (80000000 00000000)
+     rlwimi. ffffffff, 31, 31, 31 => ffffffff (80000000 00000000)
+
+     rlwinm. 00000000,  0,  0,  0 => 00000000 (20000000 00000000)
+     rlwinm. 00000000,  0,  0, 31 => 00000000 (20000000 00000000)
+     rlwinm. 00000000,  0, 31,  0 => 00000000 (20000000 00000000)
+     rlwinm. 00000000,  0, 31, 31 => 00000000 (20000000 00000000)
+     rlwinm. 00000000, 31,  0,  0 => 00000000 (20000000 00000000)
+     rlwinm. 00000000, 31,  0, 31 => 00000000 (20000000 00000000)
+     rlwinm. 00000000, 31, 31,  0 => 00000000 (20000000 00000000)
+     rlwinm. 00000000, 31, 31, 31 => 00000000 (20000000 00000000)
+     rlwinm. 000f423f,  0,  0,  0 => 00000000 (20000000 00000000)
+     rlwinm. 000f423f,  0,  0, 31 => 000f423f (40000000 00000000)
+     rlwinm. 000f423f,  0, 31,  0 => 00000001 (40000000 00000000)
+     rlwinm. 000f423f,  0, 31, 31 => 00000001 (40000000 00000000)
+     rlwinm. 000f423f, 31,  0,  0 => 80000000 (80000000 00000000)
+     rlwinm. 000f423f, 31,  0, 31 => 8007a11f (80000000 00000000)
+     rlwinm. 000f423f, 31, 31,  0 => 80000001 (80000000 00000000)
+     rlwinm. 000f423f, 31, 31, 31 => 00000001 (40000000 00000000)
+     rlwinm. ffffffff,  0,  0,  0 => 80000000 (80000000 00000000)
+     rlwinm. ffffffff,  0,  0, 31 => ffffffff (80000000 00000000)
+     rlwinm. ffffffff,  0, 31,  0 => 80000001 (80000000 00000000)
+     rlwinm. ffffffff,  0, 31, 31 => 00000001 (40000000 00000000)
+     rlwinm. ffffffff, 31,  0,  0 => 80000000 (80000000 00000000)
+     rlwinm. ffffffff, 31,  0, 31 => ffffffff (80000000 00000000)
+     rlwinm. ffffffff, 31, 31,  0 => 80000001 (80000000 00000000)
+     rlwinm. ffffffff, 31, 31, 31 => 00000001 (40000000 00000000)
+
+      rlwnm. 00000000, 00000000,  0,  0 => 00000000 (20000000 00000000)
+      rlwnm. 00000000, 00000000,  0, 31 => 00000000 (20000000 00000000)
+      rlwnm. 00000000, 00000000, 31,  0 => 00000000 (20000000 00000000)
+      rlwnm. 00000000, 00000000, 31, 31 => 00000000 (20000000 00000000)
+      rlwnm. 00000000, 000f423f,  0,  0 => 00000000 (20000000 00000000)
+      rlwnm. 00000000, 000f423f,  0, 31 => 00000000 (20000000 00000000)
+      rlwnm. 00000000, 000f423f, 31,  0 => 00000000 (20000000 00000000)
+      rlwnm. 00000000, 000f423f, 31, 31 => 00000000 (20000000 00000000)
+      rlwnm. 00000000, ffffffff,  0,  0 => 00000000 (20000000 00000000)
+      rlwnm. 00000000, ffffffff,  0, 31 => 00000000 (20000000 00000000)
+      rlwnm. 00000000, ffffffff, 31,  0 => 00000000 (20000000 00000000)
+      rlwnm. 00000000, ffffffff, 31, 31 => 00000000 (20000000 00000000)
+      rlwnm. 000f423f, 00000000,  0,  0 => 00000000 (20000000 00000000)
+      rlwnm. 000f423f, 00000000,  0, 31 => 000f423f (40000000 00000000)
+      rlwnm. 000f423f, 00000000, 31,  0 => 00000001 (40000000 00000000)
+      rlwnm. 000f423f, 00000000, 31, 31 => 00000001 (40000000 00000000)
+      rlwnm. 000f423f, 000f423f,  0,  0 => 80000000 (80000000 00000000)
+      rlwnm. 000f423f, 000f423f,  0, 31 => 8007a11f (80000000 00000000)
+      rlwnm. 000f423f, 000f423f, 31,  0 => 80000001 (80000000 00000000)
+      rlwnm. 000f423f, 000f423f, 31, 31 => 00000001 (40000000 00000000)
+      rlwnm. 000f423f, ffffffff,  0,  0 => 80000000 (80000000 00000000)
+      rlwnm. 000f423f, ffffffff,  0, 31 => 8007a11f (80000000 00000000)
+      rlwnm. 000f423f, ffffffff, 31,  0 => 80000001 (80000000 00000000)
+      rlwnm. 000f423f, ffffffff, 31, 31 => 00000001 (40000000 00000000)
+      rlwnm. ffffffff, 00000000,  0,  0 => 80000000 (80000000 00000000)
+      rlwnm. ffffffff, 00000000,  0, 31 => ffffffff (80000000 00000000)
+      rlwnm. ffffffff, 00000000, 31,  0 => 80000001 (80000000 00000000)
+      rlwnm. ffffffff, 00000000, 31, 31 => 00000001 (40000000 00000000)
+      rlwnm. ffffffff, 000f423f,  0,  0 => 80000000 (80000000 00000000)
+      rlwnm. ffffffff, 000f423f,  0, 31 => ffffffff (80000000 00000000)
+      rlwnm. ffffffff, 000f423f, 31,  0 => 80000001 (80000000 00000000)
+      rlwnm. ffffffff, 000f423f, 31, 31 => 00000001 (40000000 00000000)
+      rlwnm. ffffffff, ffffffff,  0,  0 => 80000000 (80000000 00000000)
+      rlwnm. ffffffff, ffffffff,  0, 31 => ffffffff (80000000 00000000)
+      rlwnm. ffffffff, ffffffff, 31,  0 => 80000001 (80000000 00000000)
+      rlwnm. ffffffff, ffffffff, 31, 31 => 00000001 (40000000 00000000)
+
+      srawi. 00000000,  0 => 00000000 (20000000 00000000)
+      srawi. 00000000, 31 => 00000000 (20000000 00000000)
+      srawi. 000f423f,  0 => 000f423f (40000000 00000000)
+      srawi. 000f423f, 31 => 00000000 (20000000 00000000)
+      srawi. ffffffff,  0 => ffffffff (80000000 00000000)
+      srawi. ffffffff, 31 => ffffffff (80000000 20000000)
+
+        mcrf 0, 0 (00000000) => (00000000 00000000)
+        mcrf 0, 7 (00000000) => (00000000 00000000)
+        mcrf 7, 0 (00000000) => (00000000 00000000)
+        mcrf 7, 7 (00000000) => (00000000 00000000)
+        mcrf 0, 0 (000f423f) => (000f423f 00000000)
+        mcrf 0, 7 (000f423f) => (f00f423f 00000000)
+        mcrf 7, 0 (000f423f) => (000f4230 00000000)
+        mcrf 7, 7 (000f423f) => (000f423f 00000000)
+        mcrf 0, 0 (ffffffff) => (ffffffff 00000000)
+        mcrf 0, 7 (ffffffff) => (ffffffff 00000000)
+        mcrf 7, 0 (ffffffff) => (ffffffff 00000000)
+        mcrf 7, 7 (ffffffff) => (ffffffff 00000000)
+
+       mcrxr 0 (00000000) => (00000000 00000000)
+       mcrxr 1 (00000000) => (00000000 00000000)
+       mcrxr 2 (00000000) => (00000000 00000000)
+       mcrxr 3 (00000000) => (00000000 00000000)
+       mcrxr 4 (00000000) => (00000000 00000000)
+       mcrxr 5 (00000000) => (00000000 00000000)
+       mcrxr 6 (00000000) => (00000000 00000000)
+       mcrxr 7 (00000000) => (00000000 00000000)
+       mcrxr 0 (10000000) => (00000000 00000000)
+       mcrxr 1 (10000000) => (00000000 00000000)
+       mcrxr 2 (10000000) => (00000000 00000000)
+       mcrxr 3 (10000000) => (00000000 00000000)
+       mcrxr 4 (10000000) => (00000000 00000000)
+       mcrxr 5 (10000000) => (00000000 00000000)
+       mcrxr 6 (10000000) => (00000000 00000000)
+       mcrxr 7 (10000000) => (00000000 00000000)
+       mcrxr 0 (20000000) => (20000000 00000000)
+       mcrxr 1 (20000000) => (02000000 00000000)
+       mcrxr 2 (20000000) => (00200000 00000000)
+       mcrxr 3 (20000000) => (00020000 00000000)
+       mcrxr 4 (20000000) => (00002000 00000000)
+       mcrxr 5 (20000000) => (00000200 00000000)
+       mcrxr 6 (20000000) => (00000020 00000000)
+       mcrxr 7 (20000000) => (00000002 00000000)
+       mcrxr 0 (30000000) => (20000000 00000000)
+       mcrxr 1 (30000000) => (02000000 00000000)
+       mcrxr 2 (30000000) => (00200000 00000000)
+       mcrxr 3 (30000000) => (00020000 00000000)
+       mcrxr 4 (30000000) => (00002000 00000000)
+       mcrxr 5 (30000000) => (00000200 00000000)
+       mcrxr 6 (30000000) => (00000020 00000000)
+       mcrxr 7 (30000000) => (00000002 00000000)
+       mcrxr 0 (40000000) => (40000000 00000000)
+       mcrxr 1 (40000000) => (04000000 00000000)
+       mcrxr 2 (40000000) => (00400000 00000000)
+       mcrxr 3 (40000000) => (00040000 00000000)
+       mcrxr 4 (40000000) => (00004000 00000000)
+       mcrxr 5 (40000000) => (00000400 00000000)
+       mcrxr 6 (40000000) => (00000040 00000000)
+       mcrxr 7 (40000000) => (00000004 00000000)
+       mcrxr 0 (50000000) => (40000000 00000000)
+       mcrxr 1 (50000000) => (04000000 00000000)
+       mcrxr 2 (50000000) => (00400000 00000000)
+       mcrxr 3 (50000000) => (00040000 00000000)
+       mcrxr 4 (50000000) => (00004000 00000000)
+       mcrxr 5 (50000000) => (00000400 00000000)
+       mcrxr 6 (50000000) => (00000040 00000000)
+       mcrxr 7 (50000000) => (00000004 00000000)
+       mcrxr 0 (60000000) => (60000000 00000000)
+       mcrxr 1 (60000000) => (06000000 00000000)
+       mcrxr 2 (60000000) => (00600000 00000000)
+       mcrxr 3 (60000000) => (00060000 00000000)
+       mcrxr 4 (60000000) => (00006000 00000000)
+       mcrxr 5 (60000000) => (00000600 00000000)
+       mcrxr 6 (60000000) => (00000060 00000000)
+       mcrxr 7 (60000000) => (00000006 00000000)
+       mcrxr 0 (70000000) => (60000000 00000000)
+       mcrxr 1 (70000000) => (06000000 00000000)
+       mcrxr 2 (70000000) => (00600000 00000000)
+       mcrxr 3 (70000000) => (00060000 00000000)
+       mcrxr 4 (70000000) => (00006000 00000000)
+       mcrxr 5 (70000000) => (00000600 00000000)
+       mcrxr 6 (70000000) => (00000060 00000000)
+       mcrxr 7 (70000000) => (00000006 00000000)
+       mcrxr 0 (80000000) => (80000000 00000000)
+       mcrxr 1 (80000000) => (08000000 00000000)
+       mcrxr 2 (80000000) => (00800000 00000000)
+       mcrxr 3 (80000000) => (00080000 00000000)
+       mcrxr 4 (80000000) => (00008000 00000000)
+       mcrxr 5 (80000000) => (00000800 00000000)
+       mcrxr 6 (80000000) => (00000080 00000000)
+       mcrxr 7 (80000000) => (00000008 00000000)
+       mcrxr 0 (90000000) => (80000000 00000000)
+       mcrxr 1 (90000000) => (08000000 00000000)
+       mcrxr 2 (90000000) => (00800000 00000000)
+       mcrxr 3 (90000000) => (00080000 00000000)
+       mcrxr 4 (90000000) => (00008000 00000000)
+       mcrxr 5 (90000000) => (00000800 00000000)
+       mcrxr 6 (90000000) => (00000080 00000000)
+       mcrxr 7 (90000000) => (00000008 00000000)
+       mcrxr 0 (a0000000) => (a0000000 00000000)
+       mcrxr 1 (a0000000) => (0a000000 00000000)
+       mcrxr 2 (a0000000) => (00a00000 00000000)
+       mcrxr 3 (a0000000) => (000a0000 00000000)
+       mcrxr 4 (a0000000) => (0000a000 00000000)
+       mcrxr 5 (a0000000) => (00000a00 00000000)
+       mcrxr 6 (a0000000) => (000000a0 00000000)
+       mcrxr 7 (a0000000) => (0000000a 00000000)
+       mcrxr 0 (b0000000) => (a0000000 00000000)
+       mcrxr 1 (b0000000) => (0a000000 00000000)
+       mcrxr 2 (b0000000) => (00a00000 00000000)
+       mcrxr 3 (b0000000) => (000a0000 00000000)
+       mcrxr 4 (b0000000) => (0000a000 00000000)
+       mcrxr 5 (b0000000) => (00000a00 00000000)
+       mcrxr 6 (b0000000) => (000000a0 00000000)
+       mcrxr 7 (b0000000) => (0000000a 00000000)
+       mcrxr 0 (c0000000) => (c0000000 00000000)
+       mcrxr 1 (c0000000) => (0c000000 00000000)
+       mcrxr 2 (c0000000) => (00c00000 00000000)
+       mcrxr 3 (c0000000) => (000c0000 00000000)
+       mcrxr 4 (c0000000) => (0000c000 00000000)
+       mcrxr 5 (c0000000) => (00000c00 00000000)
+       mcrxr 6 (c0000000) => (000000c0 00000000)
+       mcrxr 7 (c0000000) => (0000000c 00000000)
+       mcrxr 0 (d0000000) => (c0000000 00000000)
+       mcrxr 1 (d0000000) => (0c000000 00000000)
+       mcrxr 2 (d0000000) => (00c00000 00000000)
+       mcrxr 3 (d0000000) => (000c0000 00000000)
+       mcrxr 4 (d0000000) => (0000c000 00000000)
+       mcrxr 5 (d0000000) => (00000c00 00000000)
+       mcrxr 6 (d0000000) => (000000c0 00000000)
+       mcrxr 7 (d0000000) => (0000000c 00000000)
+       mcrxr 0 (e0000000) => (e0000000 00000000)
+       mcrxr 1 (e0000000) => (0e000000 00000000)
+       mcrxr 2 (e0000000) => (00e00000 00000000)
+       mcrxr 3 (e0000000) => (000e0000 00000000)
+       mcrxr 4 (e0000000) => (0000e000 00000000)
+       mcrxr 5 (e0000000) => (00000e00 00000000)
+       mcrxr 6 (e0000000) => (000000e0 00000000)
+       mcrxr 7 (e0000000) => (0000000e 00000000)
+       mcrxr 0 (f0000000) => (e0000000 00000000)
+       mcrxr 1 (f0000000) => (0e000000 00000000)
+       mcrxr 2 (f0000000) => (00e00000 00000000)
+       mcrxr 3 (f0000000) => (000e0000 00000000)
+       mcrxr 4 (f0000000) => (0000e000 00000000)
+       mcrxr 5 (f0000000) => (00000e00 00000000)
+       mcrxr 6 (f0000000) => (000000e0 00000000)
+       mcrxr 7 (f0000000) => (0000000e 00000000)
+
+       mtcrf   0, 00000000 => (00000000 00000000)
+       mtcrf  99, 00000000 => (00000000 00000000)
+       mtcrf 198, 00000000 => (00000000 00000000)
+       mtcrf   0, 000f423f => (00000000 00000000)
+       mtcrf  99, 000f423f => (0000003f 00000000)
+       mtcrf 198, 000f423f => (00000230 00000000)
+       mtcrf   0, ffffffff => (00000000 00000000)
+       mtcrf  99, ffffffff => (0ff000ff 00000000)
+       mtcrf 198, ffffffff => (ff000ff0 00000000)
+
+PPC integer load insns
+    with one register + one 16 bits immediate args with flags update:
+         lbz  0, (00000000) => 00000000,  0 (00000000 00000000)
+         lbz  3, (000f423f) => 00000000,  0 (00000000 00000000)
+         lbz  7, (ffffffff) => 0000003f,  0 (00000000 00000000)
+         lbz  1, (ffffffff) => 000000ff,  0 (00000000 00000000)
+         lbz -3, (000f423f) => 0000000f,  0 (00000000 00000000)
+         lbz -7, (00000000) => 00000000,  0 (00000000 00000000)
+
+        lbzu  0, (00000000) => 00000000,  0 (00000000 00000000)
+        lbzu  3, (000f423f) => 00000000,  3 (00000000 00000000)
+        lbzu  7, (ffffffff) => 0000003f,  7 (00000000 00000000)
+        lbzu  1, (ffffffff) => 000000ff,  1 (00000000 00000000)
+        lbzu -3, (000f423f) => 0000000f, -3 (00000000 00000000)
+        lbzu -7, (00000000) => 00000000, -7 (00000000 00000000)
+
+         lha  0, (00000000) => 00000000,  0 (00000000 00000000)
+         lha  3, (000f423f) => 00000000,  0 (00000000 00000000)
+         lha  7, (ffffffff) => 00003fff,  0 (00000000 00000000)
+         lha  1, (ffffffff) => ffffffff,  0 (00000000 00000000)
+         lha -3, (000f423f) => 00000f42,  0 (00000000 00000000)
+         lha -7, (00000000) => 00000000,  0 (00000000 00000000)
+
+        lhau  0, (00000000) => 00000000,  0 (00000000 00000000)
+        lhau  3, (000f423f) => 00000000,  3 (00000000 00000000)
+        lhau  7, (ffffffff) => 00003fff,  7 (00000000 00000000)
+        lhau  1, (ffffffff) => ffffffff,  1 (00000000 00000000)
+        lhau -3, (000f423f) => 00000f42, -3 (00000000 00000000)
+        lhau -7, (00000000) => 00000000, -7 (00000000 00000000)
+
+         lhz  0, (00000000) => 00000000,  0 (00000000 00000000)
+         lhz  3, (000f423f) => 00000000,  0 (00000000 00000000)
+         lhz  7, (ffffffff) => 00003fff,  0 (00000000 00000000)
+         lhz  1, (ffffffff) => 0000ffff,  0 (00000000 00000000)
+         lhz -3, (000f423f) => 00000f42,  0 (00000000 00000000)
+         lhz -7, (00000000) => 00000000,  0 (00000000 00000000)
+
+        lhzu  0, (00000000) => 00000000,  0 (00000000 00000000)
+        lhzu  3, (000f423f) => 00000000,  3 (00000000 00000000)
+        lhzu  7, (ffffffff) => 00003fff,  7 (00000000 00000000)
+        lhzu  1, (ffffffff) => 0000ffff,  1 (00000000 00000000)
+        lhzu -3, (000f423f) => 00000f42, -3 (00000000 00000000)
+        lhzu -7, (00000000) => 00000000, -7 (00000000 00000000)
+
+         lwz  0, (00000000) => 00000000,  0 (00000000 00000000)
+         lwz  3, (000f423f) => 00000f42,  0 (00000000 00000000)
+         lwz  7, (ffffffff) => 3fffffff,  0 (00000000 00000000)
+         lwz  1, (ffffffff) => ffffff00,  0 (00000000 00000000)
+         lwz -3, (000f423f) => 0f423fff,  0 (00000000 00000000)
+         lwz -7, (00000000) => 00000000,  0 (00000000 00000000)
+
+        lwzu  0, (00000000) => 00000000,  0 (00000000 00000000)
+        lwzu  3, (000f423f) => 00000f42,  3 (00000000 00000000)
+        lwzu  7, (ffffffff) => 3fffffff,  7 (00000000 00000000)
+        lwzu  1, (ffffffff) => ffffff00,  1 (00000000 00000000)
+        lwzu -3, (000f423f) => 0f423fff, -3 (00000000 00000000)
+        lwzu -7, (00000000) => 00000000, -7 (00000000 00000000)
+
+PPC integer load insns with two register args:
+        lbzx 0 (00000000) => 00000000, 0 (00000000 00000000)
+        lbzx 4 (000f423f) => 00000000, 0 (00000000 00000000)
+        lbzx 8 (ffffffff) => 000000ff, 0 (00000000 00000000)
+
+       lbzux 0 (00000000) => 00000000, 0 (00000000 00000000)
+       lbzux 4 (000f423f) => 00000000, 4 (00000000 00000000)
+       lbzux 8 (ffffffff) => 000000ff, 8 (00000000 00000000)
+
+        lhax 0 (00000000) => 00000000, 0 (00000000 00000000)
+        lhax 4 (000f423f) => 0000000f, 0 (00000000 00000000)
+        lhax 8 (ffffffff) => ffffffff, 0 (00000000 00000000)
+
+       lhaux 0 (00000000) => 00000000, 0 (00000000 00000000)
+       lhaux 4 (000f423f) => 0000000f, 4 (00000000 00000000)
+       lhaux 8 (ffffffff) => ffffffff, 8 (00000000 00000000)
+
+        lhzx 0 (00000000) => 00000000, 0 (00000000 00000000)
+        lhzx 4 (000f423f) => 0000000f, 0 (00000000 00000000)
+        lhzx 8 (ffffffff) => 0000ffff, 0 (00000000 00000000)
+
+       lhzux 0 (00000000) => 00000000, 0 (00000000 00000000)
+       lhzux 4 (000f423f) => 0000000f, 4 (00000000 00000000)
+       lhzux 8 (ffffffff) => 0000ffff, 8 (00000000 00000000)
+
+        lwzx 0 (00000000) => 00000000, 0 (00000000 00000000)
+        lwzx 4 (000f423f) => 000f423f, 0 (00000000 00000000)
+        lwzx 8 (ffffffff) => ffffffff, 0 (00000000 00000000)
+
+       lwzux 0 (00000000) => 00000000, 0 (00000000 00000000)
+       lwzux 4 (000f423f) => 000f423f, 4 (00000000 00000000)
+       lwzux 8 (ffffffff) => ffffffff, 8 (00000000 00000000)
+
+PPC integer store insns
+    with one register + one 16 bits immediate args with flags update:
+         stb 00000000,  0 => 00000000,  0 (00000000 00000000)
+         stb 000f423f,  4 => 3f000000,  0 (00000000 00000000)
+         stb ffffffff,  8 => ff000000,  0 (00000000 00000000)
+         stb 00000000, -8 => 00000000,  0 (00000000 00000000)
+         stb 000f423f, -4 => 3f000000,  0 (00000000 00000000)
+         stb ffffffff,  0 => ff000000,  0 (00000000 00000000)
+
+        stbu 00000000,  0 => 00000000,  0 (00000000 00000000)
+        stbu 000f423f,  4 => 3f000000,  4 (00000000 00000000)
+        stbu ffffffff,  8 => ff000000,  8 (00000000 00000000)
+        stbu 00000000, -8 => 00000000, -8 (00000000 00000000)
+        stbu 000f423f, -4 => 3f000000, -4 (00000000 00000000)
+        stbu ffffffff,  0 => ff000000,  0 (00000000 00000000)
+
+         sth 00000000,  0 => 00000000,  0 (00000000 00000000)
+         sth 000f423f,  4 => 423f0000,  0 (00000000 00000000)
+         sth ffffffff,  8 => ffff0000,  0 (00000000 00000000)
+         sth 00000000, -8 => 00000000,  0 (00000000 00000000)
+         sth 000f423f, -4 => 423f0000,  0 (00000000 00000000)
+         sth ffffffff,  0 => ffff0000,  0 (00000000 00000000)
+
+        sthu 00000000,  0 => 00000000,  0 (00000000 00000000)
+        sthu 000f423f,  4 => 423f0000,  4 (00000000 00000000)
+        sthu ffffffff,  8 => ffff0000,  8 (00000000 00000000)
+        sthu 00000000, -8 => 00000000, -8 (00000000 00000000)
+        sthu 000f423f, -4 => 423f0000, -4 (00000000 00000000)
+        sthu ffffffff,  0 => ffff0000,  0 (00000000 00000000)
+
+         stw 00000000,  0 => 00000000,  0 (00000000 00000000)
+         stw 000f423f,  4 => 000f423f,  0 (00000000 00000000)
+         stw ffffffff,  8 => ffffffff,  0 (00000000 00000000)
+         stw 00000000, -8 => 00000000,  0 (00000000 00000000)
+         stw 000f423f, -4 => 000f423f,  0 (00000000 00000000)
+         stw ffffffff,  0 => ffffffff,  0 (00000000 00000000)
+
+        stwu 00000000,  0 => 00000000,  0 (00000000 00000000)
+        stwu 000f423f,  4 => 000f423f,  4 (00000000 00000000)
+        stwu ffffffff,  8 => ffffffff,  8 (00000000 00000000)
+        stwu 00000000, -8 => 00000000, -8 (00000000 00000000)
+        stwu 000f423f, -4 => 000f423f, -4 (00000000 00000000)
+        stwu ffffffff,  0 => ffffffff,  0 (00000000 00000000)
+
+PPC integer store insns with three register args:
+        stbx 00000000, 0 => 00000000, 0 (00000000 00000000)
+        stbx 000f423f, 4 => 3f000000, 0 (00000000 00000000)
+        stbx ffffffff, 8 => ff000000, 0 (00000000 00000000)
+
+       stbux 00000000, 0 => 00000000, 0 (00000000 00000000)
+       stbux 000f423f, 4 => 3f000000, 4 (00000000 00000000)
+       stbux ffffffff, 8 => ff000000, 8 (00000000 00000000)
+
+        sthx 00000000, 0 => 00000000, 0 (00000000 00000000)
+        sthx 000f423f, 4 => 423f0000, 0 (00000000 00000000)
+        sthx ffffffff, 8 => ffff0000, 0 (00000000 00000000)
+
+       sthux 00000000, 0 => 00000000, 0 (00000000 00000000)
+       sthux 000f423f, 4 => 423f0000, 4 (00000000 00000000)
+       sthux ffffffff, 8 => ffff0000, 8 (00000000 00000000)
+
+        stwx 00000000, 0 => 00000000, 0 (00000000 00000000)
+        stwx 000f423f, 4 => 000f423f, 0 (00000000 00000000)
+        stwx ffffffff, 8 => ffffffff, 0 (00000000 00000000)
+
+       stwux 00000000, 0 => 00000000, 0 (00000000 00000000)
+       stwux 000f423f, 4 => 000f423f, 4 (00000000 00000000)
+       stwux ffffffff, 8 => ffffffff, 8 (00000000 00000000)
+
+All done. Tested 92 different instructions

Added: trunk/none/tests/ppc32/jm-int_other.vgtest
==============================================================================
--- trunk/none/tests/ppc32/jm-int_other.vgtest (added)
+++ trunk/none/tests/ppc32/jm-int_other.vgtest Wed May  3 19:15:01 2017
@@ -0,0 +1 @@
+prog: jm-insns -l -L -c

Added: trunk/none/tests/ppc32/test_isa_2_06_part2-div.stderr.exp
==============================================================================
--- trunk/none/tests/ppc32/test_isa_2_06_part2-div.stderr.exp (added)
+++ trunk/none/tests/ppc32/test_isa_2_06_part2-div.stderr.exp Wed May  3 19:15:01 2017
@@ -0,0 +1,2 @@
+
+

Added: trunk/none/tests/ppc32/test_isa_2_06_part2-div.stdout.exp
==============================================================================
--- trunk/none/tests/ppc32/test_isa_2_06_part2-div.stdout.exp (added)
+++ trunk/none/tests/ppc32/test_isa_2_06_part2-div.stdout.exp Wed May  3 19:15:01 2017
@@ -0,0 +1,31 @@
+Test div extensions
+#0: divweu: 0x00000000 / 0x00000002 = 0x00000000; CR=0; XER=0
+#1: divweu: 0x00000002 / 0x00000000 = 0x00000000; CR=0; XER=0
+#2: divweu: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=0; XER=0
+#3: divweu: 0xfabc1234 / 0x00000005 = 0x00000000; CR=0; XER=0
+#4: divweu: 0x0000004d / 0x00000042 = 0x00000000; CR=0; XER=0
+#5: divweu: 0x00000005 / 0xfabc1234 = 0x00000005; CR=0; XER=0
+
+#0: divweu.: 0x00000000 / 0x00000002 = 0x00000000; CR=2; XER=0
+#1: divweu.: 0x00000002 / 0x00000000 = 0x00000000; CR=2; XER=0
+#2: divweu.: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=8; XER=0
+#3: divweu.: 0xfabc1234 / 0x00000005 = 0x00000000; CR=2; XER=0
+#4: divweu.: 0x0000004d / 0x00000042 = 0x00000000; CR=2; XER=0
+#5: divweu.: 0x00000005 / 0xfabc1234 = 0x00000005; CR=4; XER=0
+
+
+#0: divweuo: 0x00000000 / 0x00000002 = 0x00000000; CR=0; XER=0
+#1: divweuo: 0x00000002 / 0x00000000 = 0x00000000; CR=0; XER=c0000000
+#2: divweuo: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=0; XER=0
+#3: divweuo: 0xfabc1234 / 0x00000005 = 0x00000000; CR=0; XER=c0000000
+#4: divweuo: 0x0000004d / 0x00000042 = 0x00000000; CR=0; XER=c0000000
+#5: divweuo: 0x00000005 / 0xfabc1234 = 0x00000005; CR=0; XER=0
+
+#0: divweuo.: 0x00000000 / 0x00000002 = 0x00000000; CR=2; XER=0
+#1: divweuo.: 0x00000002 / 0x00000000 = 0x00000000; CR=3; XER=c0000000
+#2: divweuo.: 0x7abc1234 / 0xf0000000 = 0x82eabe15; CR=8; XER=0
+#3: divweuo.: 0xfabc1234 / 0x00000005 = 0x00000000; CR=3; XER=c0000000
+#4: divweuo.: 0x0000004d / 0x00000042 = 0x00000000; CR=3; XER=c0000000
+#5: divweuo.: 0x00000005 / 0xfabc1234 = 0x00000005; CR=4; XER=0
+
+

Added: trunk/none/tests/ppc32/test_isa_2_06_part2-div.vgtest
==============================================================================
--- trunk/none/tests/ppc32/test_isa_2_06_part2-div.vgtest (added)
+++ trunk/none/tests/ppc32/test_isa_2_06_part2-div.vgtest Wed May  3 19:15:01 2017
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_ppc64_auxv_cap arch_2_06
+prog: test_isa_2_06_part2 -d

Added: trunk/none/tests/ppc32/test_isa_2_06_part3-div.stderr.exp
==============================================================================
--- trunk/none/tests/ppc32/test_isa_2_06_part3-div.stderr.exp (added)
+++ trunk/none/tests/ppc32/test_isa_2_06_part3-div.stderr.exp Wed May  3 19:15:01 2017
@@ -0,0 +1,2 @@
+
+

Added: trunk/none/tests/ppc32/test_isa_2_06_part3-div.stdout.exp
==============================================================================
--- trunk/none/tests/ppc32/test_isa_2_06_part3-div.stdout.exp (added)
+++ trunk/none/tests/ppc32/test_isa_2_06_part3-div.stdout.exp Wed May  3 19:15:01 2017
@@ -0,0 +1,31 @@
+Test div extensions
+#0: divwe: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=0; XER=0
+#1: divwe: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=0; XER=0
+#2: divwe: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=0; XER=0
+#3: divwe: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=0; XER=0
+#4: divwe: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=0; XER=0
+#5: divwe: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=0; XER=0
+
+#0: divwe.: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=2; XER=0
+#1: divwe.: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=2; XER=0
+#2: divwe.: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=2; XER=0
+#3: divwe.: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=2; XER=0
+#4: divwe.: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=2; XER=0
+#5: divwe.: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=8; XER=0
+
+
+#0: divweo: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=0; XER=0
+#1: divweo: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=0; XER=c0000000
+#2: divweo: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=0; XER=c0000000
+#3: divweo: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=0; XER=c0000000
+#4: divweo: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=0; XER=c0000000
+#5: divweo: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=0; XER=0
+
+#0: divweo.: 0x0000000000000000 / 0x00000002 = 0x00000000; CR=2; XER=0
+#1: divweo.: 0x0000000200000000 / 0x00000000 = 0x00000000; CR=3; XER=c0000000
+#2: divweo.: 0x7abc123400000000 / 0xf0000000 = 0x00000000; CR=3; XER=c0000000
+#3: divweo.: 0xfabc123400000000 / 0x00000005 = 0x00000000; CR=3; XER=c0000000
+#4: divweo.: 0x0000004d00000000 / 0x00000042 = 0x00000000; CR=3; XER=c0000000
+#5: divweo.: 0x0000000500000000 / 0xfabc1234 = 0xffffff0d; CR=8; XER=0
+
+

Added: trunk/none/tests/ppc32/test_isa_2_06_part3-div.vgtest
==============================================================================
--- trunk/none/tests/ppc32/test_isa_2_06_part3-div.vgtest (added)
+++ trunk/none/tests/ppc32/test_isa_2_06_part3-div.vgtest Wed May  3 19:15:01 2017
@@ -0,0 +1,2 @@
+prereq: ../../../tests/check_ppc64_auxv_cap arch_2_06
+prog: test_isa_2_06_part3  -d

Added: trunk/none/tests/ppc64/jm-int.stdout.exp-LE-ISA3_0
==============================================================================
--- trunk/none/tests/ppc64/jm-int.stdout.exp-LE-ISA3_0 (added)
+++ trunk/none/tests/ppc64/jm-int.stdout.exp-LE-ISA3_0 Wed May  3 19:15:01 2017
@@ -0,0 +1,796 @@
+PPC integer arith insns with two args:
+         add 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+         add 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+         add 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+         add 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
+         add 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00000000)
+         add 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 00000000)
+         add ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+         add ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 00000000)
+         add ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 00000000)
+
+        addo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+        addo 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+        addo 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+        addo 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
+        addo 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00080000)
+        addo 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 00000000)
+        addo ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+        addo ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 00000000)
+        addo ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 00000000)
+
+        addc 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+        addc 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+        addc 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+        addc 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
+        addc 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00000000)
+        addc 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 20000000)
+        addc ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+        addc ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
+        addc ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 20000000)
+
+       addco 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+       addco 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+       addco 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+       addco 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
+       addco 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00080000)
+       addco 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 20000000)
+       addco ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
+       addco ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
+       addco ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 20000000)
+
+        divw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+        divw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+        divw 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
+        divw 0000001cbe991def, ffffffffffffffff => 000000004166e211 (00000000 00000000)
+        divw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+        divw ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+       divwo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+       divwo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+       divwo 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
+       divwo 0000001cbe991def, ffffffffffffffff => 000000004166e211 (00000000 00000000)
+       divwo ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+       divwo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+       divwu 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+       divwu 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+       divwu 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
+       divwu 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+       divwu ffffffffffffffff, 0000001cbe991def => 0000000000000001 (00000000 00000000)
+       divwu ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+      divwuo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+      divwuo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+      divwuo 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
+      divwuo 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+      divwuo ffffffffffffffff, 0000001cbe991def => 0000000000000001 (00000000 00000000)
+      divwuo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+       mulhw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+       mulhw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+       mulhw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+       mulhw 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
+       mulhw 0000001cbe991def, 0000001cbe991def => 0000000010b56825 (00000000 00000000)
+       mulhw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+       mulhw ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
+       mulhw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+       mulhw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+
+      mulhwu 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+      mulhwu 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+      mulhwu 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+      mulhwu 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
+      mulhwu 0000001cbe991def, 0000001cbe991def => 000000008de7a403 (00000000 00000000)
+      mulhwu 0000001cbe991def, ffffffffffffffff => 00000000be991dee (00000000 00000000)
+      mulhwu ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
+      mulhwu ffffffffffffffff, 0000001cbe991def => 00000000be991dee (00000000 00000000)
+      mulhwu ffffffffffffffff, ffffffffffffffff => 00000000fffffffe (00000000 00000000)
+
+       mullw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+       mullw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+       mullw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+       mullw 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
+       mullw 0000001cbe991def, 0000001cbe991def => 10b568258f2e0521 (00000000 00000000)
+       mullw 0000001cbe991def, ffffffffffffffff => 000000004166e211 (00000000 00000000)
+       mullw ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
+       mullw ffffffffffffffff, 0000001cbe991def => 000000004166e211 (00000000 00000000)
+       mullw ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+      mullwo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+      mullwo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+      mullwo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+      mullwo 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
+      mullwo 0000001cbe991def, 0000001cbe991def => 10b568258f2e0521 (00000000 c0080000)
+      mullwo 0000001cbe991def, ffffffffffffffff => 000000004166e211 (00000000 00000000)
+      mullwo ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
+      mullwo ffffffffffffffff, 0000001cbe991def => 000000004166e211 (00000000 00000000)
+      mullwo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+        subf 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+        subf 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+        subf 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+        subf 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000 00000000)
+        subf 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+        subf 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 00000000)
+        subf ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000 00000000)
+        subf ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
+        subf ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+
+       subfo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+       subfo 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
+       subfo 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+       subfo 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000 00000000)
+       subfo 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+       subfo 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 00000000)
+       subfo ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000 00000000)
+       subfo ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
+       subfo ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+
+       subfc 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 20000000)
+       subfc 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 20000000)
+       subfc 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
+       subfc 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000 00000000)
+       subfc 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 20000000)
+       subfc 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 20000000)
+       subfc ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000 00000000)
+       subfc ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
+       subfc ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 20000000)
+
+      subfco 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 20000000)
+      subfco 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 20000000)
+      subfco 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
+      subfco 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000 00000000)
+      subfco 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 20000000)
+      subfco 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 20000000)
+      subfco ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000 00000000)
+      subfco ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
+      subfco ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 20000000)
+
+       mulhd 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+       mulhd 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+       mulhd 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+       mulhd 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
+       mulhd 0000001cbe991def, 0000001cbe991def => 000000000000033a (00000000 00000000)
+       mulhd 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
+       mulhd ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
+       mulhd ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
+       mulhd ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+
+      mulhdu 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+      mulhdu 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+      mulhdu 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+      mulhdu 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
+      mulhdu 0000001cbe991def, 0000001cbe991def => 000000000000033a (00000000 00000000)
+      mulhdu 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 00000000)
+      mulhdu ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
+      mulhdu ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 00000000)
+      mulhdu ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 00000000)
+
+       mulld 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+       mulld 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+       mulld 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+       mulld 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
+       mulld 0000001cbe991def, 0000001cbe991def => 3f66304b8f2e0521 (00000000 00000000)
+       mulld 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (00000000 00000000)
+       mulld ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
+       mulld ffffffffffffffff, 0000001cbe991def => ffffffe34166e211 (00000000 00000000)
+       mulld ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+      mulldo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+      mulldo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+      mulldo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+      mulldo 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
+      mulldo 0000001cbe991def, 0000001cbe991def => 3f66304b8f2e0521 (00000000 c0080000)
+      mulldo 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (00000000 00000000)
+      mulldo ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
+      mulldo ffffffffffffffff, 0000001cbe991def => ffffffe34166e211 (00000000 00000000)
+      mulldo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+        divd 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+        divd 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+        divd 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+        divd 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
+        divd 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
+        divd 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (00000000 00000000)
+        divd ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
+        divd ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+        divd ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+       divdu 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
+       divdu 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+       divdu 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+       divdu 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
+       divdu 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
+       divdu 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+       divdu ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
+       divdu ffffffffffffffff, 0000001cbe991def => 0000000008e7f283 (00000000 00000000)
+       divdu ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+       divdo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 c0080000)
+       divdo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+       divdo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+       divdo 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 c0080000)
+       divdo 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
+       divdo 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (00000000 00000000)
+       divdo ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 c0080000)
+       divdo ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+       divdo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+      divduo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 c0080000)
+      divduo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
+      divduo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+      divduo 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 c0080000)
+      divduo 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
+      divduo 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
+      divduo ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 c0080000)
+      divduo ffffffffffffffff, 0000001cbe991def => 0000000008e7f283 (00000000 00000000)
+      divduo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
+
+PPC integer arith insns with two args with flags update:
+        add. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+        add. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
+        add. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+        add. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
+        add. 0000001cbe991def, 0000001cbe991def => 000000397d323bde (40000000 00000000)
+        add. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 00000000)
+        add. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+        add. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 00000000)
+        add. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 00000000)
+
+       addo. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+       addo. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
+       addo. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+       addo. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
+       addo. 0000001cbe991def, 0000001cbe991def => 000000397d323bde (40000000 00080000)
+       addo. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 00000000)
+       addo. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+       addo. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 00000000)
+       addo. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 00000000)
+
+       addc. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+       addc. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
+       addc. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+       addc. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
+       addc. 0000001cbe991def, 0000001cbe991def => 000000397d323bde (40000000 00000000)
+       addc. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 20000000)
+       addc. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+       addc. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 20000000)
+       addc. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 20000000)
+
+      addco. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+      addco. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
+      addco. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
+      addco. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
+      addco. 0000001cbe991def, 0000001cbe991def => 000000397d323bde (40000000 00080000)
+      addco. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 20000000)
+      addco. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
+      addco. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 20000000)
+      addco. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 20000000)
+
+       divw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+       divw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+       divw. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)
+       divw. 0000001cbe991def, ffffffffffffffff => 000000004166e211 (40000000 00000000)
+       divw. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+       divw. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
+
+      divwo. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+      divwo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+      divwo. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)
+      divwo. 0000001cbe991def, ffffffffffffffff => 000000004166e211 (40000000 00000000)
+      divwo. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+      divwo. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
+
+      divwu. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+      divwu. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+      divwu. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)
+      divwu. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+      divwu. ffffffffffffffff, 0000001cbe991def => 0000000000000001 (40000000 00000000)
+      divwu. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
+
+     divwuo. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+     divwuo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+     divwuo. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)
+     divwuo. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+     divwuo. ffffffffffffffff, 0000001cbe991def => 0000000000000001 (40000000 00000000)
+     divwuo. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
+
+      mulhw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+      mulhw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+      mulhw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+      mulhw. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
+      mulhw. 0000001cbe991def, 0000001cbe991def => 0000000010b56825 (40000000 00000000)
+      mulhw. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+      mulhw. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
+      mulhw. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+      mulhw. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+
+     mulhwu. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+     mulhwu. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+     mulhwu. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+     mulhwu. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
+     mulhwu. 0000001cbe991def, 0000001cbe991def => 000000008de7a403 (80000000 00000000)
+     mulhwu. 0000001cbe991def, ffffffffffffffff => 00000000be991dee (80000000 00000000)
+     mulhwu. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
+     mulhwu. ffffffffffffffff, 0000001cbe991def => 00000000be991dee (80000000 00000000)
+     mulhwu. ffffffffffffffff, ffffffffffffffff => 00000000fffffffe (80000000 00000000)
+
+      mullw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+      mullw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+      mullw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+      mullw. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
+      mullw. 0000001cbe991def, 0000001cbe991def => 10b568258f2e0521 (40000000 00000000)
+      mullw. 0000001cbe991def, ffffffffffffffff => 000000004166e211 (40000000 00000000)
+      mullw. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
+      mullw. ffffffffffffffff, 0000001cbe991def => 000000004166e211 (40000000 00000000)
+      mullw. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
+
+     mullwo. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
+     mullwo. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
+     mullwo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
+     mullwo. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
+     mullwo. 0000001cbe991def, 0000001cbe991def => 10b568258f2e0521 (50000000 c0080000)
+     mullwo. 0000001cbe991def, ffffffffffffffff => 000000004166e211 (40000000 00000000)
+     mullwo. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
+     mullwo. ffffffffffffffff, 0000001cbe991def => 000000004166e211 (40000000 00000000)
+     mullwo. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
+

[... 8854 lines stripped ...]

------------------------------------------------------------------------------
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot
_______________________________________________
Valgrind-developers mailing list
[hidden email]
https://lists.sourceforge.net/lists/listinfo/valgrind-developers
Loading...